Pulse-based flip flop
AssigneeNational Chiao Tung University
InventorsChen-Yi Lee, Wei-Hao Sung, Ming-Che Lee
Life of this patent
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Abstract
A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a first clock signal and the second clock signal. The pulse-based flip-flop includes a pulse generator and a data latch. The pulse generator includes a first inverter and a signal delay circuit to receive the first clock signal and generate the second clock signal; the data latch includes a delivery circuit, a latch circuit and a control circuit. The data latch is used to latch the data input signal and output the data output signal in response to the first and the second clock signals.
Claims11
A pulse-based flip flop for latching a data input signal in response to a first clock signal and a second clock signal to convert the data input signal to a data output signal, the pulse-based flip flop comprising:
- a pulse generator configured for receiving the first clock signal and generating the second clock signal, the pulse generator comprising:
- a first inverter configured for receiving the first clock signal and outputting the second signal;
- a signal delay circuit electrically connected to the first inverter, configured for receiving the second clock signal and delaying the second clock signal;
- and
- a data latch in response to the first clock signal and the second clock signal, configured for latching the data input signal and generating the data output signal, the data latch comprises:
- a delivery circuit configured for delivering the data input signal;
- a latch circuit electrically connected to the delivery circuit, configured for receiving and latching the data input signal, and also outputting the data output signal;
- and
- a control circuit electrically connected to the latch circuit, configured for providing voltage to control the on and off of the latch circuit, wherein the control circuit comprises:
- a first PMOS transistor, the gate of the first PMOS transistor being configured for receiving an inverted data input signal which is the inverse of the data input signal, and the source of the first PMOS transistor being electrically connected to a power supply potential;
- a second PMOS transistor, the gate of the PMOS transistor being configured for receiving the data input signal, and the source of the PMOS transistor being electrically connected to the power supply potential;
- a third PMOS transistor, the gate of the third PMOS transistor being configured for receiving the first clock signal, the source of the third PMOS transistor being electrically connected to the drain of the first PMOS transistor or the drain of the second PMOS transistor, and the drain of the third PMOS transistor being electrically connected to the drain of the second PMOS transistor or the drain of the first PMOS transistor;
- and
- a fourth PMOS transistor, the gate of the fourth PMOS transistor being configured for receiving the second clock signal, the source of the fourth PMOS transistor being electrically connected to the source of the third PMOS transistor, and the drain of the fourth PMOS transistor being electrically connected to the drain of the third PMOS transistor.
Dependencies are inferred from the claim text.