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US 8,947,141 B2Granted
Differential amplifiers, clock generator circuits, delay lines and methods
AssigneeMicron Technology, Inc.
InventorAaron Willey
Life of this patent
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Abstract
A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.
Claims16
A clock generator, comprising:
- an input buffer configured to receive a clock signal at a signal input node and to output the clock signal at an output node;
- a delay line including an input node coupled to the output node of the input buffer, an output node, and a duty cycle control node, the delay line being configured to be responsive to a duty cycle control signal applied to the duty cycle control node to adjust a duty cycle of the clock signal being coupled through the delay line, wherein the delay line further comprises a gain control node, and wherein the delay line is configured to have a gain that is adjustable responsive to a signal applied to the gain control node;
- a phase detector having a first input node coupled to the signal output node of the delay line, a second input node coupled to receive the clock signal applied to the signal input node of the input buffer, and an output node, the phase detector being configured to adjust a delay of delay line based on a phase difference between a signal applied to the first input node and the clock signal applied to the second input node;
- and
- a duty cycle control circuit having an input node coupled to the output node of the delay line and an output node coupled to the duty cycle control node of the delay line, the duty cycle control circuit being configured to provide at the output node the duty cycle control signal corresponding to the duty cycle of the clock signal being coupled through the delay line from the input node of the delay line to the output node of the delay line.
2 more elements
A method, comprising:
- coupling a first signal through a delay line;
- examining a duty cycle of a second signal at an output of the delay line;
- and
- before or during coupling the first signal through the delay line:
- adjusting, based on the examination, the duty cycle of the first signal by adjusting a switch point of a circuit through which the first signal is coupled;
- and
- adjusting the gain of the circuit.
4 more elements
An apparatus, comprising:
- a delay line configured to receive an input signal and to provide an output signal that is delayed relative to the input signal, the delay line configured to adjust a duty cycle of the input signal to provide the output signal, wherein the delay line comprises a differential amplifier circuit and a feedback circuit, wherein the feedback circuit is configured to provide a feedback signal to the differential amplifier circuit, wherein the differential amplifier circuit is configured to adjust the duty cycle of the input signal to provide the output signal based on the feedback signal;
- and
- a duty cycle control circuit configured to control adjustment of the duty cycle of the input signal through the delay line based on a duty cycle of the output signal delayed through a feedback model circuit.
An apparatus, comprising:
- a delay line configured to receive an input signal and to provide an output signal that is delayed relative to the input signal, the delay line configured to adjust a duty cycle of the input signal to provide the output signal, wherein the delay line comprises a differential amplifier circuit that is configured to adjust the duty cycle of the input signal to provide the output signal, wherein the differential amplifier comprises:
- a first transistor configured to receive the input signal at a first gate;
- a second transistor configured to receive a second input signal at a second gate, wherein the second input signal is complementary to the input signal received at the first gate;
- a third transistor configured to receive a first control signal from the duty cycle control circuit at a third gate, wherein the adjustment of the duty cycle of the input signal is based on a value of the first control signal, wherein the output signal is provided at a node coupled to the second transistor and the third transistor;
- a fourth transistor configured to receive a second control signal at a fourth gate, wherein the second control signal is complementary to the control signal received at the third gate, and wherein the adjustment of the duty cycle of the input signal is further based on a value of the second control signal;
- a fifth transistor configured to receive a first feedback signal at a fifth gate, wherein the first feedback signal is based on the output signal;
- and
- a sixth transistor configured to receive a second feedback signal at a sixth gate, wherein the second feedback signal is complementary to the first feedback signal, wherein the adjustment of the duty cycle of the input signal is further based on values of the first feedback signal and the second feedback signal;
- and
- a duty cycle control circuit configured to control adjustment of the duty cycle of the input signal through the delay line based on a duty cycle of the output signal delayed through a feedback model circuit.
7 more elements
Dependencies are inferred from the claim text.