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US 8,947,135 B2Granted
Output circuit and voltage signal output method
AssigneeFujitsu Semiconductor Limited
InventorYuichi Itonaga
Life of this patent
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AssigneeFujitsu Semiconductor Limited
InventorYuichi Itonaga
Estimating the term…
An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power supply and an output node; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power supply and the output node; a bias voltage generation circuit outputting a first bias voltage to a first bias node connected to a gate terminal of the second PMOS transistor and a second bias voltage to a second bias node connected to a gate terminal of the second NMOS transistor; first and second bias voltage stabilization circuits suppressing fluctuations in the first and second bias voltages; and a control circuit detecting a change in a signal that fluctuates the first bias voltage and the second bias voltage and controlling the first and second bias voltage stabilization circuits.
An output circuit comprising:
A voltage signal output method for outputting a signal having an amplitude equal to or greater than a withstand voltage of a transistor by applying a first bias voltage to the gate of one PMOS transistor of two PMOS transistors and two NMOS transistors cascode-connected, by applying a second bias voltage to the gate of one of the NMOS transistors, and applying an output signal to the gates of the other one PMOS transistor and the other one NMOS transistor, the method comprising:
Dependencies are inferred from the claim text.