Decoupling circuit and semiconductor integrated circuit
AssigneeRenesas Electronics Corporation
InventorsMasatomo Eimitsu, Takanori Saeki
Life of this patent
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Abstract
A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.
Claims9
A circuit comprising:
- a first power supply line;
- a second power supply line;
- a first transistor coupled between the first and second power supply lines and having a first conductivity type;
- a second transistor coupled between the first and second power supply lines, coupled in series with the first transistor via a first node, and having a second conductivity type different from the first conductivity type,
- a third transistor coupled in parallel with the second transistor between the first node and the second power supply line, and having the second conductivity type, the second transistor and the third transistor coupled directly to the second power supply line and coupled directly to the first transistor, wherein gate terminals of the second and third transistors are coupled in common;
- a fourth transistor coupled between the first and second power supply lines and having the first conductivity type;
- a fifth transistor coupled between the first and second power supply lines, coupled in series with the fourth transistor via a second node, and having the second conductivity type, gate terminals of the fourth and fifth transistors being coupled in common with the first node;
- and
- a sixth transistor coupled in parallel with the fourth transistor between the second node and the first power supply line, and having the first conductivity type, wherein gate terminals of the fourth and sixth transistors are coupled in common, the fourth transistor and the sixth transistor coupled directly to the fifth transistor.
Dependencies are inferred from the claim text.