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US 8,947,131 B2Granted
Multi-voltage supplied input buffer
AssigneeSamsung Electronics Co., Ltd.
InventorSeungho Lee
Life of this patent
Estimating the term…
Abstract
An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage. The input buffer further includes a bias circuit configured to generate the variable voltage responsive to a state of the input signal.
Claims20
An input buffer comprising:
- a first stage which is formed of semiconductor circuit elements for a first power supply voltage, receives a variable voltage same or higher than the first power supply voltage as an operating voltage, and generates a first output signal in response to an input signal;
- and
- a second stage which is formed of a semiconductor circuit element for the first power supply voltage, receives the first power supply voltage as an operating voltage, and generates a second output signal as an input buffering output in response to the first output signal,
- wherein the variable voltage has one selected from a plurality of levels according to a level of a first state voltage of the input signal,
- wherein the first stage comprises:
- a pull-up unit which generates a pull-up output signal in response to a pull-up input signal;
- a pull-down unit which generates a pull-down output signal in response to the input signal;
- an output unit which generates a first output signal in response to the pull-up and pull-down output signals;
- and
- a first pull-up protection unit which provides the pull-up input signal to the pull-up unit in response to the input signal,
- wherein when the input signal is at a logic low state, the first pull-up protection unit provides the pull-up unit with a pull-up bias voltage, as the pull-up input signal, varied in response to a level of the variable voltage.
8 more elements
An input buffer comprising:
- an pull-up unit which is formed of a semiconductor circuit element for a first power supply voltage, receives a variable voltage same or higher than the first power supply voltage as an operating voltage, and generates a pull-up output signal in response to a pull-up input signal;
- a pull-down unit which is formed of a semiconductor circuit element for the first power supply voltage and generates a pull-down output signal in response to an input signal;
- an output unit which generates a first output signal in response to the pull-up and pull-down output signals;
- a pull-up control unit which generates the pull-up control signal in response to the input signal;
- and
- a pull-up protection unit which provides a pull-up input signal to the pull-up unit in response to the pull-up control signal,
- wherein the pull-up protection unit comprises a first pull-up protection transistor having a source connected to receive a pull-up bias voltage, a gate connected to receive a pull-up control signal, and a drain connected to output the pull-up bias voltage;
- and a second pull-up protection transistor having a drain connected with the drain of the first pull-up protection transistor, a gate connected to receive the pull-up bias voltage, and a source connected to output the pull-up input signal;
- wherein the pull-up unit comprises a pull-up transistor having a source connected to receive a variable voltage, a gate connected to receive the pull-up input signal, and a drain connected to output the pull-up output signal;
- and
- wherein the variable voltage has one selected from a plurality of levels according to a level of a first state voltage of the input signal.
8 more elements
An input buffer comprising:
- a first stage configured to generate a first output signal at an output thereof in response to an input signal, the first stage comprising semiconductor circuit components configured to be adapted to a first power supply voltage and configured to be variably biased responsive to a variable voltage, the first stage comprising:
- a pull-up control circuit configured to generate a pull-up input signal responsive to the input signal;
- a pull-up circuit having an input that receives the pull-up input signal and that is configured to selectively couple the output of the first stage to a node having the variable voltage responsive to the pull-up input signal;
- a bias circuit configured to generate a bias voltage responsive to the variable voltage;
- and
- a pull-up protection circuit coupled to the input of the pull-up circuit and configured to control a level of the pull-up input signal responsive to the bias voltage;
- a second stage configured to receive the first output signal and to responsively generate a second output signal, the second stage biased according to the first power supply voltage;
- and
- the bias circuit configured to generate the variable voltage responsive to a state of the input signal, wherein the variable voltage is same or higher than the first power supply voltage.
6 more elements
Dependencies are inferred from the claim text.