Fast, low power comparator with dynamic bias background

A method of conserving power in a comparator circuit, comprising:

• estimating a switching regulator load current value;
• communicating the load current value to a current bias generator;
• enabling the bias current generator with an enabling signal from a switching regulator PFM logic circuit;
• and
• establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling signal and the estimated load current value, comprising:
• receiving a digital signal of estimated load at a digital-to-analog converter current source, and
• setting a bias current of the operational amplifier on the basis of the digital signal of estimated load.

A non-transitory computer readable media including program instructions which when executed by a processor cause the processor to perform the method of conserving power in a comparator circuit, comprising:

• estimating a switching regulator load current value;
• communicating the load current value to a current bias generator;
• enabling the bias current generator with an enabling signal from a switching regulator PFM logic circuit;
• and
• establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling signal and the estimated current value, comprising:
• receiving a digital signal of estimated load at a digital-to-analog converter current source, and
• setting a bias current of the operational amplifier on the basis of the digital signal of estimated load.

A comparator circuit comprising:

• means for comparing a difference between a switching voltage (Vsw) and a reference voltage (Vref);
• and
• means for dynamically adjusting a bias current to the comparing means, comprising:
• means to receive a pulse frequency modulation enabling signal, and
• means for converting a digital estimated current signal to output the analog bias current to the comparing means.