Clock gater with independently programmable delay
AssigneeAdvanced Micro Devices, Inc.
InventorsDeepesh John, Teja Singh, Sundar Rangarajan
Life of this patent
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Abstract
An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.
Claims20
An integrated circuit device comprising:
- first circuitry comprising first logic devices and a clock tree configured to distribute a clock signal to the first logic devices;
- and
- second circuitry comprising second logic devices, a first clock gater and a second clock gater,
- wherein each of the first and second clock gaters comprises a programmable delay circuit including a plurality of delay elements, each element configured to impose a different amount of delay,
- wherein each of the first and second clock gaters is operable to receive the clock signal and configurable to distribute the clock signal to the second logic devices through one of the plurality of delay elements, and
- wherein the first clock gater is operable to distribute the clock signal to a first subset of the second logic devices and the second clock gater is operable to distribute the clock signal to a second subset of the second logic devices.
A method, comprising:
- distributing a clock signal through a clock tree to first logic devices in a first circuitry;
- and
- distributing the clock signal to second logic devices in a second circuitry,
- wherein the second circuitry comprises a first clock gater and a second clock gater, wherein each of the first and second clock gaters comprises a programmable delay circuit including a plurality of delay elements, each element imposing a different amount of delay,
- wherein distributing the clock signal comprises configuring each of the first and second clock gaters to receive and distribute the clock signal to the second logic devices through one of the plurality of delay elements, and
- wherein the first clock gater is configured to distribute the clock signal to a first subset of the second logic devices and the second clock gater is configured to distribute the clock signal to a second subset of the second logic devices.
A computer-readable storage medium having instructions stored thereon, execution of which by a processor cause the processor to perform operations, the operations causing a manufacturing facility to create an apparatus comprising:
- first circuitry including first logic devices and a clock tree configured to distribute a clock signal to the first logic devices;
- and
- second circuitry comprising second logic devices, a first clock gater and a second clock gater, wherein each of the first and second clock gaters comprises a programmable delay circuit including a plurality of delay elements, each element configured to impose a different amount of delay,
- wherein each of the first and second clock gaters is operable to receive the clock signal and configurable to distribute the clock signal to the second logic devices through one of the plurality of delay elements, and
- wherein the first clock gater is operable to distribute the clock signal to a first subset of the second logic devices and the second clock gater is operable to distribute the clock signal to a second subset of the second logic devices.
Dependencies are inferred from the claim text.