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US 8,947,123 B2Granted
Wave dynamic differential logic
AssigneeThe Regents of the University of California
InventorsIngrid Verbauwhede, Kris J. V. Tiri
Life of this patent
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Abstract
Wave Dynamic Differential Logic (WDDL) is provided, wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a WDDL stage, etc. In one embodiment, a Divided Wave Dynamic Differential Logic (DWDDL) is provided wherein a WDDL circuit is conveniently implemented as dual logic trees.
Claims24
A method of operating a logic circuit, comprising:
- during a pre-charge phase associated with a logic tree comprising a plurality of interconnected differential logic gates:
- receiving a pre-charge wave at at least first and second inputs of a first differential logic gate of the plurality of interconnected differential logic gates;
- propagating the pre-charge wave from the first and second inputs of the first differential logic gate to at least first and second outputs of the first differential logic gate;
- receiving the pre-charge wave propagated by the first differential logic gate at at least first and second inputs of a second differential logic gate of the plurality of interconnected differential logic gates, the second differential logic gate subsequent to the first differential logic gate in the logic tree;
- propagating the received pre-charge wave from the first and second inputs of the second differential logic gate to at least first and second outputs of the second differential logic gate,
- wherein the first and second differential logic gates do not include separate pre-charge signal inputs.
3 more elements
A method of operating a logic circuit, comprising:
- during a pre-discharge phase associated with a logic tree comprising a plurality of interconnected differential logic gates:
- receiving a pre-discharge wave at at least first and second inputs of a first differential logic gate of the plurality of interconnected differential logic gates;
- propagating the pre-discharge wave from the first and second inputs of the first differential logic gate to at least first and second outputs of the first differential logic gate;
- receiving the pre-discharge wave propagated by the first differential logic gate at at least first and second inputs of a second differential logic gate of the plurality of interconnected differential logic gates, the second differential logic gate subsequent to the first differential logic gate in the logic tree;
- propagating the received pre-discharge wave from the first and second inputs of the second differential logic gate to at least first and second outputs of the second differential logic gate,
- wherein the first and second differential logic gates do not include separate pre-discharge signal inputs.
3 more elements
A logic circuit, comprising:
- a logic tree comprising a plurality of interconnected logic gates, the plurality of interconnected differential logic gates comprising:
- a first differential logic gate comprising at least first and second inputs and at least first and second outputs, the first differential logic gate configured, during a pre-charge phase associated with the logic tree, to:
- receive a pre-charge wave on the first and second inputs of the first differential logic gate;
- and
- propagate the received pre-charge wave to the first and second outputs of the first differential logic gate, wherein the first output of the first differential logic gate is pre-charged to the same value as the second output of the first differential logic gate;
- and
- a second differential logic gate subsequent to the first differential logic gate in the logic tree, comprising at least first and second inputs and at least first and second outputs, and configured, during the pre-charge phase, to:
- receive, on the first and second inputs of the second differential logic gate, the pre-charge wave propagated by the first differential logic gate;
- and
- propagate the pre-charge wave to the first and second outputs of the second differential logic gate, wherein the first output of the second differential logic gate is pre-charged to the same value as the second output of the second differential logic gate.
7 more elements
A logic circuit, comprising:
- a logic tree comprising a plurality of interconnected differential logic gates, the plurality of interconnected differential logic gates comprising:
- a first differential logic gate comprising at least first and second inputs and at least first and second outputs, the first differential logic gate configured, during a pre-discharge phase associated with the logic tree, to:
- receive a pre-discharge wave on the first and second inputs of the first differential logic gate;
- and
- propagate the received pre-discharge wave to the first and second outputs of the first differential logic gate, wherein the first output of the first differential logic gate is pre-discharged to the same value as the second output of the first differential logic gate;
- and
- a second differential logic gate subsequent to the first differential logic gate in the logic tree, comprising at least first and second inputs and at least first and second outputs, configured, during the pre-discharge phase, to:
- receive on the first and second inputs of the second differential logic gate, the pre-discharge wave propagated by the first differential logic gate;
- and
- propagate the pre-discharge wave to the first and second outputs of the second differential logic gate, wherein the first output of the second differential logic gate is pre-discharged to the same value as the second output of the second differential logic gate.
7 more elements
Dependencies are inferred from the claim text.