Non-volatile latch structures with small area for FPGA
AssigneeCypress Semiconductor Corporation
InventorVenkatraman Prabhakar
Life of this patent
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Abstract
A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit.
Claims20
A latch circuit comprising:
- a first non-volatile tri-gate device coupled between a source of supply voltage and an output node;
- and
- a second non-volatile tri-gate device including a first end and a second end, wherein the first end is coupled to the first non-volatile tri-gate at the output node and the second end is coupled to ground.
A latch circuit comprising:
- a first non-volatile tri-gate device coupled between a first node and a bit line;
- a second non-volatile tri-gate device coupled between a second node and a source line;
- and
- a cross-coupled circuit coupled to a source of supply voltage, wherein the cross-coupled circuit is further coupled to the first non-volatile tri-gate at the first node and to the second non-volatile tri-gate at the second node.
A method of operating a non-volatile latch circuit, the method comprising:
- providing a first tri-gate non-volatile device;
- providing a second tri-gate non-volatile device;
- coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, wherein the coupling of the first and second tri-gate non-volatile devices is disposed within the non-volatile latch circuit;
- erasing the first tri-gate non-volatile device;
- programming the second tri-gate non-volatile device;
- and
- latching an output node of the latch circuit to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices.
Dependencies are inferred from the claim text.