Back to results
US 8,947,120 B2Granted
Latch array utilizing through device connectivity
AssigneeApple Inc.
InventorsMichael R. Seningen, Gregory D. Roberts, Robert Kenney, James De Leon
Life of this patent
Estimating the term…
Abstract
A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.
Claims25
A latch array, comprising:
- a circuit configured to generate a control signal;
- and
- a plurality of standard cells configured to receive and store data;
- wherein respective portions of a plurality of logic devices included in the plurality of standard cells that are coupled to the control signal are aligned;
- and
- wherein the control signal is routed using a single layer conductive material uni-directionally to interconnect the plurality of logic devices.
3 more elements
A system, comprising:
- a processing unit, and
- one or more latch arrays, wherein each of the latch arrays comprises:
- a circuit configured to generate a control signal;
- and
- a plurality of latch circuits configured to receive and store data;
- wherein respective portions of a plurality of logic devices included in the plurality of latch circuits that are coupled to the control signal are aligned;
- and
- wherein the control signal is routed using a single layer conductive material uni-directionally to interconnect the plurality of logic devices.
5 more elements
A bit slice logic circuit, comprising:
- a circuit configured to generate a control signal;
- and
- a plurality of logic gates, wherein each given logic gate is configured to operate on a respective portion of a data word;
- wherein respective portions of a plurality of logic devices included in the plurality of gates that are coupled to the control signal are aligned;
- and
- wherein the control signal is routed using a single layer conductive material uni-directionally to interconnect the plurality of logic devices.
3 more elements
A system, comprising:
- a processing unit;
- a test unit configured to generate a global test signal;
- and
- a plurality of bit slice functional blocks, wherein each bit slice functional block comprises:
- a local test circuit configured to generate a local test signal dependent upon the global test signal;
- a plurality of logic gates, wherein each give logic gate is configured to operate on a respective portion of a data word;
- wherein respective portions of a plurality of logic devices included in the plurality of gates are coupled to the local test signal are aligned;
- and
- wherein the local test signal is routed using a single layer conductive material uni-directionally to interconnect the plurality of logic devices.
6 more elements
An apparatus, comprising:
- a control unit [or circuit] configured to generate a control signal;
- and
- a plurality of standard cells configured to receive and store data, wherein the plurality of standard cells includes a plurality of logic devices coupled to the control signal;
- and
- wherein respective portions of the plurality of logic devices include a particular alignment such that a single layer conductive material uni-directionally interconnects the control signal to the plurality of logic devices.
2 more elements
Dependencies are inferred from the claim text.