Electronic device, and open circuit detecting system, detecting method thereof

A method for detecting open circuit comprising the steps of:

• providing an open circuit detecting system to connect to an object circuit for acquiring an electrical signal through a virtual ground induced by characteristic impedance of a parasitic capacitor, wherein the open circuit detecting system comprises a test unit, a stray-capacitance boosting unit, a sampling unit, and a signal processing unit;
• wherein the sampling unit is a sampling resistor, the signal processing unit comprises an inverter, a comparator connected to the inverter, and an “AND” gate connected to the comparator, the test unit is connected to the stray-capacitance boosting unit, a second input of the stray-capacitance boosting unit is connected to the object circuit, an output of the stray-capacitance boosting unit is connected to the sampling resistor, an input of the inverter is connected to the common point of the stray-capacitance boosting unit and the sampling resistor, an output of the inverter is connected to a negative terminal of the comparator, an positive terminal of the comparator is configured to receive a reference voltage, an output of the comparator is connected to a first input of the “AND” gate, a second input of the “AND” gate is configured to receive a gate pulse;
• and
• determining whether the object circuit is open according to the electrical signal.

A method for detecting open circuit comprising the steps of:

• connecting a parasitic capacitor to a virtual ground through characteristic impedance of the parasitic capacitor;
• providing an open circuit detecting system for testing the capacitance of the parasitic capacitor and generating an electrical signal representing the capacitance of the parasitic capacitor, wherein the open circuit detecting system comprises a test unit, a stray-capacitance boosting unit, a sampling unit, and a signal processing unit;
• wherein the sampling unit is a sampling resistor, the signal processing unit comprises an inverter, a comparator connected to the inverter, and an “AND” gate connected to the comparator, the test unit is connected to the stray-capacitance boosting unit, a second input of the stray-capacitance boosting unit is connected to the object circuit, an output of the stray-capacitance boosting unit is connected to the sampling resistor, an input of the inverter is connected to the common point of the stray-capacitance boosting unit and the sampling resistor, an output of the inverter is connected to a negative terminal of the comparator, an positive terminal of the comparator is configured to receive a reference voltage, an output of the comparator is connected to a first input of the “AND” gate, a second input of the “AND” gate is configured to receive a gate pulse;
• and
• determining whether the object circuit is open according to the electrical signal.

An electronic device, comprising:

• an object circuit;
• and
• an open circuit detecting system connected to the object circuit for getting an electrical signal through a virtual ground induced by characteristic impedance of a parasitic capacitor and determining whether the object circuit is open or not electrically connected to the open circuit detecting system according to the electrical signal, wherein the open circuit detecting system comprises a test unit, a stray-capacitance boosting unit, a sampling unit, and a signal processing unit;
• wherein the sampling unit is a sampling resistor, the signal processing unit comprises an inverter, a comparator connected to the inverter, and an “AND” gate connected to the comparator, the test unit is connected to the stray-capacitance boosting unit, a second input of the stray-capacitance boosting unit is connected to the object circuit, an output of the stray-capacitance boosting unit is connected to the sampling resistor, an input of the inverter is connected to the common point of the stray-capacitance boosting unit and the sampling resistor, an output of the inverter is connected to a negative terminal of the comparator, an positive terminal of the comparator is configured to receive a reference voltage, an output of the comparator is connected to a first input of the “AND” gate, a second input of the “AND” gate is configured to receive a gate pulse.