Contact power rail
AssigneeGlobalfoundries Inc.
InventorsJason Eugene Stephens, Marc L. Tarabbia, Nader Magdy Hindawy, Roderick Alan Augur
Life of this patent
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Abstract
A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.
Claims13
A method comprising:
- forming a horizontal diffusion contact (CA) power rail in an active layer of a semiconductor substrate using a first color mask;
- forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail,
- wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches;
- and
- wherein the first, second, and third color masks are of different colors and provide an indication of an acceptable design by avoiding same color space violations.
A method comprising:
- forming first and second horizontal diffusion regions (RX) in an RX layer of a semiconductor substrate within a cell;
- forming a first, second, third, and fourth vertical polysilicon gate electrodes (PCs), evenly spaced in a PC layer of the semiconductor substrate;
- forming a horizontal positive power rail (VDD) in a metal layer (M1) of the semiconductor substrate;
- forming a horizontal negative power rail (VSS) in the M1 layer;
- forming first and second horizontal diffusion contact (CA) power rails in a CA layer of the semiconductor substrate, above VDD and VSS, respectively;
- forming a plurality of pairs of vertical CAs in the CA layer, each vertical CA attached to an RX region, evenly spaced between VDD and VSS;
- forming a plurality of vias (R0) connecting the first and second horizontal CA power rails with the M1 layer, each R0 above a vertical PC and within a horizontal CA power rail;
- and
- forming a first and a second horizontal gate cut region (CT) between the PCs and the first and second horizontal CA power rails, respectively,
- wherein the horizontal CA power rails and the vertical CAs are decomposed into a first color mask and second and third color masks, respectively, and
- wherein the first, second, and third color masks are of different colors and provide an indication of an acceptable design by avoiding same color space violations.
Dependencies are inferred from the claim text.