Multilayer wiring substrate and method of manufacturing the same
AssigneeNgk Spark Plug Co., Ltd.
InventorShinnosuke Maeda
Life of this patent
Estimating the term…
Abstract
To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
Claims15
A multilayer wiring substrate comprising:
- an interlayer insulation layer isolating a lower conductor layer from an upper conductor layer;
- via holes formed in the interlayer insulation layer;
- and
- via conductors formed in the respective via holes for connecting the lower conductor layer and the upper conductor layer;
- wherein:
- the via holes open at a surface of the interlayer insulation layer;
- stepped portions are formed in opening verge regions of the surface around the via holes such that the stepped portions are recessed from peripheral regions of the interlayer insulation layer around the opening verge regions;
- the surface of the interlayer insulation layer, which includes the stepped portions and the peripheral regions, is a rough surface;
- the stepped portions are higher in surface roughness than the peripheral regions;
- the upper conductor layer comprises lands connected to upper ends of the corresponding via conductors continuously;
- and
- the via conductors and the upper conductor layers cover a top surface of the stepped portions and a top surface of the peripheral regions.
A multilayer wiring substrate comprising:
- an interlayer insulation layer;
- via conductors charged into via holes formed in the interlayer insulation layer;
- terminal pads embedded in a terminal pad side of the interlayer insulation layer;
- and
- an interlayer wiring formed on a surface of an interlayer wiring side of the interlayer insulation layer that is opposite the terminal pad side, the interlayer wiring being connected to the terminal pads via the via conductors;
- wherein:
- the via holes are shaped such that their diameters increase from the terminal pad side toward the interlayer wiring side;
- stepped portions are formed in respective opening verge regions of the surface of the interlayer insulation layer around the via holes such that the stepped portions are recessed from peripheral regions of the surface of the interlayer insulation layer around the opening verge regions;
- the stepped portions and the peripheral regions include a rough surface, and the stepped portions are higher in surface roughness than the peripheral regions;
- the interlayer wiring includes lands connected to upper ends of the via conductors continuously;
- and
- the lands cover a top surface of the stepped portion and a top surface of the peripheral regions.
A method of manufacturing a multilayer wiring substrate, comprising:
- an interlayer insulation layer forming step of forming an interlayer insulation layer which covers a lower conductor layer;
- a laser irradiation step of irradiating predetermined via hole formation positions of the interlayer insulation layer with a laser beam having a first laser energy to form via holes in the interlayer insulation layer, and irradiating predetermined stepped portion formation positions of the interlayer insulation layer in opening verge regions of a surface of the interlayer insulation layer around the via holes with a laser beam having a second laser energy weaker than the first laser energy such that the stepped portion are recessed from peripheral regions of the interlayer insulation layer around the opening verge regions;
- and
- a roughening step of roughening, after the laser irradiation step, the interlayer insulation layer so as to make an entire surface of the interlayer insulation layer, including the stepped portions and the peripheral regions, a rough surface such that surfaces of the stepped portions are higher in surface roughness than the peripheral regions;
- a via conductor forming step of forming, after the roughening step, via conductors in the respective via holes for connecting the lower conductor layer and an upper conductor layer, the via holes opening at the rough surface of the interlayer insulation layer;
- and
- an upper conductor layer forming step of forming, after the via conductor forming step, the upper conductor layer that includes lands connected to upper ends of the corresponding via conductors continuously, wherein
- the via conductors and the upper conductor layers cover a top surface of the stepped portions and a top surface of the peripheral regions.
Dependencies are inferred from the claim text.