X-line routing for dense multi-chip-package interconnects
AssigneeIntel Corporation
InventorsZhiguo Qian, Kemal Aygun
Life of this patent
Estimating the term…
Abstract
X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.
Claims14
A semiconductor package, comprising:
- first and second adjacent semiconductor dies;
- a silicon bridge structure electrically coupling the first and second semiconductor dies, and comprising a plurality of layers of conductive traces disposed above a substrate of the silicon bridge structure, a first pair of ground traces disposed in a first of the plurality of layers of conductive traces, a signal trace disposed in a second of the plurality of layers of conductive traces, below the first layer, and a second pair of ground traces disposed in a third of the plurality of layers of conductive traces, below the first layer and the second layer, wherein the first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective;
- and
- a plurality of package routing layers, wherein the silicon bridge structure is disposed in one of the package routing layers, the first and second die are disposed on the plurality of package routing layers, and at least one of the first and second die is electrically coupled to the plurality of package routing layers.
A semiconductor package, comprising:
- first and second adjacent semiconductor dies;
- an embedded interconnect bridge (EmIB) structure electrically coupling the first and second semiconductor dies, and comprising a plurality of layers of conductive traces disposed above a substrate of the EmIB structure, a first pair of ground traces disposed in a first of the plurality of layers of conductive traces, a signal trace disposed in a second of the plurality of layers of conductive traces, below the first layer, and a second pair of ground traces disposed in a third of the plurality of layers of conductive traces, below the first layer and the second layer, wherein the first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective;
- and
- a flexible organic substrate or epoxy board, wherein the EmIB structure is disposed in the flexible organic substrate or epoxy board, and the first and second semiconductor dies are disposed on the flexible organic substrate or epoxy board.
Dependencies are inferred from the claim text.