Extended liner for localized thick copper interconnect
AssigneeSTMicroelectronics S.r.l.
InventorsDavid Moreau, Jerome Ciavatti
Life of this patent
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Abstract
A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.
Claims21
A semiconductor structure, comprising:
- a semiconductor substrate;
- a dielectric layer overlying the semiconductor substrate;
- a barrier layer overlying the dielectric layer, the barrier layer having a first width;
- and
- an electrically conductive interconnect positioned over and in contact with the barrier layer, the electrically conductive interconnect having a second width that is substantially less than the first width and a height of 5 to 50 microns, wherein the difference in widths between the barrier layer and the electrically conductive interconnect is sufficient to prevent the barrier layer from undercutting the electrically conductive interconnect during formation of the semiconductor structure.
An electronic device formed on a semiconductor substrate, comprising:
- a copper interconnect, the copper interconnect having a first width and a first height, the first height being at least 2 microns;
- a barrier liner positioned beneath the copper interconnect, the barrier liner having a second width and a second height, the second width being greater than the first width;
- and
- a dielectric layer positioned beneath the barrier liner and above the semiconductor substrate.
A semiconductor structure, comprising:
- a semiconductor substrate;
- a dielectric layer overlying the semiconductor substrate;
- a barrier layer overlying the dielectric layer, the barrier layer having a first width, the first width being uniform throughout the barrier layer;
- and
- a copper interconnect formed over and in contact with the barrier layer, the copper interconnect having a second width that is narrower than the first width and a height of at least 5 microns.
Dependencies are inferred from the claim text.