Power/ground layout for chips
AssigneeMarvell World Trade Ltd.
InventorsSehat Sutardja, Chung Chyung Han, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu
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Abstract
Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
Claims15
A chip comprising:
- a base metal layer formed over a first semiconductor die;
- a first metal layer that is separate from the base metal layer, the first metal layer having a plurality of islands individually surrounded along their entire periphery by a dielectric material, wherein the plurality of islands are configured to route at least one of (i) a ground signal or (ii) a power signal in the chip;
- and
- a second metal layer that is separate from the first metal layer, the second metal layer having a plurality of islands individually surrounded along their entire periphery by a passivation material, wherein the plurality of islands are configured to route at least one of (i) the ground signal or (ii) the power signal in the chip,
- wherein the plurality of islands of the first metal layer is configured to align with the plurality of islands of the second metal layer, and
- wherein at least some of the plurality of islands of the first metal layer are connected to at least some of the plurality of islands of the second metal layer by vias.
A chip comprising:
- a base metal layer formed over a first semiconductor die;
- a first metal layer that is separate from the base metal layer, the first metal layer including (i) a first layer portion and (ii) a first island portion, wherein the first island portion is separated from the first layer portion by a first channel that surrounds the first island portion along the entire periphery of the first island portion;
- and
- a second metal layer that is separate from the first metal layer, the second metal layer including (i) a second layer portion and (ii) a second island portion, wherein the second island portion is separated from the second layer portion by a second channel that surrounds the second island portion along the entire periphery of the second island portion, wherein the first island portion of the first metal layer is (i) configured to align with the second island portion of the second metal layer, and (ii) connected to the second island portion of the second metal layer by a via.
Dependencies are inferred from the claim text.