IC in-process solution to reduce thermal neutrons soft error rate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYung-Huei Lee, Chou-Jie Tsai, Chia-Fang Wu, Wei-Cheng Chu
Life of this patent
Estimating the term…
Abstract
Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.
Claims19
An integrated circuit comprising:
- a substrate layer having an active device disposed thereon;
- a dielectric layer disposed over the active device;
- a metal layer disposed over the dielectric layer, the metal layer electrically connected to the active device by metal features disposed in the dielectric layer;
- and
- a protection layer on top of the metal layer and in physical contact with the metal layer, wherein a first portion of the protection layer contains a thermal neutron absorbing material that is an elemental impurity selected from the group consisting of Gd, Sm, Cd, and combinations thereof, wherein the first portion of protection layer extends past the metal layer and contacts a topmost surface of the dielectric layer, and wherein at least a portion of the thermal neutron absorbing material is disposed below a topmost surface of the metal layer.
An integrated circuit (IC) comprising:
- a substrate layer;
- a transistor disposed in the substrate layer;
- an intermetal dielectric layer disposed over the transistor;
- a metal layer having a bottommost surface on the topmost surface of the intermetal dielectric layer, wherein the metal layer is in electrical communication with the transistor;
- and
- a passivation layer on the metal layer, the passivation layer in physical contact with the metal layer and the intermetal dielectric layer, wherein the passivation layer is doped substantially throughout with a thermal neutron absorbing material that is an elemental impurity selected from the group consisting of Gd, Sm, Cd, and combinations thereof.
An integrated circuit (IC) comprising:
- a substrate layer;
- a metal layer above the substrate layer;
- a passivation layer on the metal layer and in physical contact with the metal layer;
- and
- a protection layer above the passivation layer and in physical contact with the passivation layer, wherein the protection layer comprises an oxide layer over the passivation layer, wherein the protection further comprises a polyimide layer over the oxide layer, wherein the oxide layer contains a thermal neutron absorbing material that is an elemental impurity selected from the group consisting of Gd, Sm, Cd, and combinations thereof.
Dependencies are inferred from the claim text.