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US 8,946,868 B2Granted
Multiple die layout for facilitating the combining of an individual die into a single die
AssigneeSilicon Laboratories Inc.
InventorsKa Y. Leung, Jean-Luc Nauleau
Life of this patent
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Abstract
A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.
Claims10
A packaged integrated circuit, comprising:
- a lead frame having a plurality of pins associated therewith;
- a combination die mounted on the lead frame and including:
- at least first and second independent integrated circuits sharing a common bulk semiconductor substrate and each having separate and independent power supply interconnect meshes associated therewith to distribute power to circuitry thereon and bonding pads for independent power connection to the associated meshes;
- and
- at least one interconnect between the at least first and second independent integrated circuit interfaced with circuitry on each of the at least first and second independent integrated circuits;
- bond wires for interfacing select portions of the circuitry of each of the first and second independent integrated circuits to select ones of the pins;
- and
- an encapsulating material for encapsulating the lead frame, the combination die and at least a portion of the pins.
5 more elements
Dependencies are inferred from the claim text.