Decoupling capacitors for integrated circuits

An integrated circuit device, comprising:

• a silicon substrate;
• analog circuitry formed on the silicon substrate;
• a digital core formed on the silicon substrate separate from the analog circuitry, the digital core including at least one area of active digital circuitry;
• one or more decoupling cell rows formed on the silicon substrate within the at least one area of active digital circuitry, each of the one or more decoupling cell rows including at least one p-type doped well or n-type doped well extending across an entire height of the decoupling cell row;
• and
• one or more metal-oxide-semiconductor (MOS) decoupling capacitors formed within the at least one p-type doped well or n-type doped well of each of the decoupling cell rows;
• where the at least one area of active digital circuitry of the digital core comprises multiple areas of active digital circuitry within an outer boundary of the digital core, each of the active digital circuitry areas including active digital circuitry and decoupling cell rows formed therein;
• where the active digital circuitry of each of the active digital circuitry areas has a different current density during circuit operation;
• and where a spacing of the decoupling cell rows in the active digital circuitry areas varies across the digital core such that a spurious noise content is substantially homogenous across the digital core during circuit operation.

An integrated circuit device, comprising:

• a silicon substrate;
• analog circuitry formed on the silicon substrate;
• a digital core formed on the silicon substrate separate from the analog circuitry, the digital core including at least one area of active digital circuitry;
• one or more decoupling cell rows formed on the silicon substrate within the at least one area of active digital circuitry, each of the one or more decoupling cell rows including at least one p-type doped well or n-type doped well extending across an entire height of the decoupling cell row;
• and
• one or more metal-oxide-semiconductor (MOS) decoupling capacitors formed within the at least one p-type doped well or n-type doped well of each of the decoupling cell rows;
• where the at least one area of active digital circuitry of the digital core comprises multiple areas of active digital circuitry within an outer boundary of the digital core, each of the active digital circuitry areas including decoupling cell rows formed therein;
• where each of the active digital circuitry areas produces a different amount of spurious noise content during circuit operation;
• and where the active digital circuitry areas that produce a relatively greatest amount of spurious noise content during circuit operation are placed within the digital core such that the active digital circuitry areas that produce the relatively greatest amount of spurious noise content during circuit operation are positioned at a greater distance from the analog circuitry than the digital circuitry areas that produce a relatively lesser amount of spurious noise content during circuit operation.

A method for configuring an integrated circuit device, comprising:

• providing a silicon substrate;
• forming analog circuitry on the silicon substrate;
• forming a digital core on the silicon substrate separate from the analog circuitry, the digital core including at least one area of active digital circuitry;
• forming one or more decoupling cell rows on the silicon substrate within the at least one area of active digital circuitry, each of the one or more decoupling cell rows including only one of a p-type doped well or an n-type doped well;
• and
• forming one or more metal-oxide-semiconductor (MOS) decoupling capacitors in the p-type doped well or n-type doped well of each of the one or more decoupling cell rows;
• forming standard cell rows on the silicon substrate within the digital core and oriented in a parallel relationship to the one or more decoupling cell rows such that one or more of the decoupling cell rows are disposed between adjacent rows of the multiple standard cell rows, each of the multiple standard cell rows including a p-type doped well and an n-type doped well;
• and
• forming the at least one p-type doped well or n-type doped well of each of the one or more decoupling cell rows to extend across an entire height of the decoupling cell row and into each of the adjacent row of the multiple standard cell rows such that the p-type doped well or n-type doped well of the decoupling cell row also forms the p-type doped well or n-type doped well of each of the adjacent standard cell rows.

A method for configuring an integrated circuit device, comprising:

• providing a silicon substrate;
• forming analog circuitry on the silicon substrate;
• forming a digital core on the silicon substrate separate from the analog circuitry, the digital core including at least one area of active digital circuitry;
• forming one or more decoupling cell rows on the silicon substrate within the at least one area of active digital circuitry, each of the one or more decoupling cell rows including only one of a p-type doped well or an n-type doped well extending across an entire height of the decoupling cell row;
• forming one or more metal-oxide-semiconductor (MOS) decoupling capacitors in the p-type doped well or n-type doped well of each of the decoupling cell rows;
• and
• forming the digital core such that the at least one area of active digital circuitry of the digital core comprises multiple areas of active digital circuitry within an outer boundary of the digital core, each of the active digital circuitry areas including active digital circuitry and decoupling cell rows formed therein;
• where each of the active digital circuitry areas has a different current density during circuit operation;
• and where the method further comprises varying a spacing the decoupling cell rows formed in the active digital circuitry areas across the digital core such that a spurious noise content is substantially homogenous across the digital core during circuit operation.

A method for configuring an integrated circuit device, comprising:

• providing a silicon substrate;
• forming analog circuitry on the silicon substrate;
• forming a digital core on the silicon substrate separate from the analog circuitry, the digital core including at least one area of active digital circuitry;
• forming one or more decoupling cell rows on the silicon substrate within the at least one area of active digital circuitry, each of the one or more decoupling cell rows including only one of a p-type doped well or an n-type doped well extending across an entire height of the decoupling cell row;
• forming one or more metal-oxide-semiconductor (MOS) decoupling capacitors in the p-type doped well or n-type doped well of each of the decoupling cell rows;
• and
• forming the digital core such that the at least one area of active digital circuitry of the digital core comprises multiple areas of active digital circuitry within an outer boundary of the digital core, each of the active digital circuitry areas including decoupling cell rows formed therein;
• where each of the active digital circuitry areas produces a different amount of spurious noise content during circuit operation;
• and where the method further comprises placing the active digital circuitry areas that produce a relatively greatest amount of spurious noise content during circuit operation within the digital core such that the active digital circuitry areas that produce the relatively greatest amount of spurious noise content during circuit operation are positioned at a greater distance from the analog circuitry than the digital circuitry areas that produce a relatively lesser amount of spurious noise content during circuit operation.