Semiconductor device having elevated structure and method of manufacturing the same

A semiconductor device, comprising:

• a semiconductor substrate having at least an active area on a top surface thereof;
• a gate stack formed over the active area, said active area further comprising source and drain regions adjacent the gate stack;
• a spacer formed on sidewalls of the gate stack;
• an elevated contact structure extending upwardly from the source or drain region to have a top surface higher than a top surface of the gate stack;
• a protection layer overlying the top surface of the gate stack, the top surface of the elevated contact structure, and the spacer, the protection layer filling at least a portion of a space formed between the top surface of the elevated contact structure and the top surface of the gate stack;
• a dielectric layer overlying the protection layer, the dielectric layer comprising a material different from a material of the protection layer;
• and
• a contact hole extending from a top surface of the dielectric layer, through the dielectric layer, through a partial thickness of the protection layer, and to the top surface of the elevated contact structure without reaching the spacer;
• wherein the elevated contact structure comprises
• a contact metal in direct electrical contact with the source or drain region and having a top surface coelevational with the top surface of the gate stack, the contact metal comprising a first metal;
• and
• a metal layer overlying the contact metal to define the top surface of the elevated contact structure, the metal layer comprising a second metal different from the first metal.

A method of forming a semiconductor device from a gate replacement structure comprising a gate stack overlying an active area on a top surface of a semiconductor substrate, a spacer on sidewalls of the gate stack, and a dielectric layer overlying the substrate around the gate stack and the spacer, said active area further comprising source and drain regions adjacent the gate stack, said method comprising:

• forming a contact opening in the dielectric layer over the source or drain region on the top surface of the substrate;
• filling a conductive material in the contact opening;
• forming a conductive elevated structure on the conductive material filled in the contact opening such that a top surface of the elevated structure is higher than a top surface of the gate stack;
• forming a protection layer, after said forming the elevated structure, on the gate stack and the spacer to fill at least a portion of a space formed between the top surface of the elevated structure and the top surface of the gate stack;
• forming a further dielectric layer over the protection layer;
• etching a further contact opening through the further dielectric layer, wherein said etching stops when the top surface of the elevated structure is exposed without reaching the top surface of the gate stack;
• and
• filling the further contact opening with a further conductive material without causing short circuit with the gate stack.

A method of manufacturing a semiconductor device, comprising:

• forming a gate stack over an active area in a top surface of a semiconductor substrate;
• forming a spacer on sidewalls of the gate stack;
• removing a top portion of the gate stack such that a top surface of the spacer is higher than a top surface of a resulting gate stack;
• and
• forming a protection layer on the resulting gate stack to fill at least a portion of a space surrounded by the spacer on the top surface of the resulting gate stack;
• wherein the method further comprises:
• before the removal of the top portion of the gate stack, forming a dummy layer over the substrate and around the spacer and the gate stack, to protect source and drain regions which are formed in the active area and adjacent the gate stack;
• after the removal of the top portion of the gate stack, removing the dummy layer to expose the source and drain regions;
• and
• performing a silicidation process on the exposed source and drain regions before the formation of the protection layer over the resulting gate stack, the spacer and the silicided source and drain regions.

A method of manufacturing a semiconductor device, comprising:

• forming a gate stack over an active area in a top surface of a semiconductor substrate;
• forming a spacer on sidewalls of the gate stack;
• removing a top portion of the gate stack such that a top surface of the spacer is higher than a top surface of a resulting gate stack;
• and
• forming a protection layer on the resulting gate stack to fill at least a portion of a space surrounded by the spacer on the top surface of the resulting gate stack;
• wherein
• the gate stack includes a gate electrode, a dummy gate on top the gate electrode, and a hard mask on top the dummy gate, wherein the hard mask projects upwardly beyond the spacer;
• said removing includes removing the hard mask and then removing the dummy gate;
• and
• during the removal of the hard mask, the hard mask and an upper portion of the spacer are simultaneously removed until the dummy gate is exposed.