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US 8,946,825 B2Granted
Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDavid Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
Life of this patent
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Abstract
During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
Claims20
An integrated circuit (IC) structure, comprising:
- a deep n-well (DNW) in a substrate;
- a p-channel metal-oxide-semiconductor (PMOS) transistor formed inside the DNW;
- an NMOS transistor formed in the substrate and outside the DNW;
- a dissipation device in the substrate, wherein the dissipation device is connected to a substrate pickup;
- and
- an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor, wherein the dissipation device is also connected to the electrical path.
3 more elements
An integrated circuit (IC) structure, comprising:
- a deep n-well (DNW) in a substrate;
- a p-channel metal-oxide-semiconductor (PMOS) transistor formed inside the DNW;
- an NMOS transistor formed in the substrate and outside the DNW;
- a dissipation device in the substrate, wherein the dissipation device is connected to a substrate pickup;
- and
- an electrical path between a gate structure of the PMOS transistor and a drain of the NMOS transistor, wherein the dissipation device is also connected to the electrical path.
3 more elements
An integrated circuit (IC) structure, comprising:
- a deep n-well (DNW) in a substrate;
- a first metal-oxide-semiconductor (MOS) transistor of a first conductivity type formed in the substrate;
- a second MOS transistor of a second conductivity type, opposite the first conductivity type, formed in the substrate, wherein one of the first MOS transistor or the second MOS transistor is inside the DNW, and one of the first MOS transistor or the second MOS transistor is outside the DNW, wherein the second MOS transistor is in an n-well in the substrate;
- a dissipation device in the substrate, wherein the dissipation device is in the n-well;
- and
- an electrical path between a drain of the first MOS transistor and a gate structure of the second MOS transistor, wherein the dissipation device is also connected to the electrical path.
3 more elements
Dependencies are inferred from the claim text.