Ultrahigh density vertical NAND memory device
AssigneeSanDisk Technologies LLC
InventorJohann Alsmeier
Life of this patent
Estimating the term…
Abstract
Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
Claims12
A monolithic three dimensional NAND string, comprising:
- a semiconductor channel located over a substrate, the semiconductor channel having a U-shaped side cross section, wherein two wing portions of the U-shaped semiconductor channel which extend substantially perpendicular to a major surface of the substrate are connected by a connecting portion which extends substantially parallel to the major surface of the substrate;
- an insulating fill located over the connecting portion and separating two wing portions of the U-shaped semiconductor channel;
- a plurality control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the substrate and below the first device level;
- a blocking dielectric is located in contact with the plurality of control gate electrodes;
- a charge storage material;
- and
- a tunneling dielectric located between the charge storage material and the semiconductor channel.
A monolithic, three dimensional array of memory devices located over a silicon substrate, comprising an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level, wherein at least one vertically oriented NAND string of the array of vertically oriented NAND strings comprises:
- a semiconductor channel located over the silicon substrate, the semiconductor channel having a U-shaped side cross section, wherein two wing portions of the U-shaped semiconductor channel which extend substantially perpendicular to a major surface of the silicon substrate are connected by a connecting portion which extends substantially parallel to the major surface of the silicon substrate;
- an insulating fill located over the connecting portion and separating two wing portions of the U-shaped semiconductor channel;
- a plurality control gate electrodes extending substantially parallel to the major surface of the silicon substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the silicon substrate and below the first device level;
- a blocking dielectric is located in contact with the plurality of control gate electrodes;
- a charge storage material;
- a tunneling dielectric located between the charge storage material and the semiconductor channel;
- and
- an integrated circuit comprising a driver circuit for the memory array located on the silicon substrate.
Dependencies are inferred from the claim text.