US 8,946,809 B2Granted

Method for manufacturing semiconductor memory device and semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorsKazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda

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Abstract

According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.

Claims20

Dependent claims

A method for manufacturing a semiconductor memory device, comprising:

forming a first stopper film on a substrate;
forming a lower gate layer on the first stopper film;
making a recess in the lower gate layer;
filling a sacrificial film into the recess;
forming a second stopper film on the sacrificial film and on the lower gate layer;
making an opening in the second stopper film to expose a portion of the sacrificial film;
forming a stacked body on the second stopper film, the stacked body including a plurality of electrode films and a plurality of insulating films provided respectively between the electrode films;
making a slit in the stacked body to reach the second stopper film;
forming an insulating separation film inside the slit;
making a hole in the stacked body to reach the first stopper film by piercing the stacked body and the opening;
removing the sacrificial film via the hole;
forming a memory film including a charge storage film on a side wall of the hole;
and
forming a channel body on a side wall of the memory film,
an etching rate of the first stopper film and the second stopper film being lower than an etching rate of the electrode films and the insulating films in the etching to make the slit and the etching to make the hole.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/017,472Filed 4 Sep 2013
Priority: JP 2013-06111222 Mar 2013
Published: US 2014/0284691 A125 Sep 2014
Granted: 3 Feb 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors