3D memory
AssigneeMicron Technology, Inc.
InventorsJohn Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
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Abstract
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.
Claims32
A vertical memory comprising:
- a stack of memory cells, a cell of the stack comprising:
- a control gate;
- a charge storage structure having a dimension;
- a barrier film between the charge storage structure and the control gate, wherein the barrier film has a dimension corresponding to the dimension of the charge storage structure, and wherein the dimension of the charge storage structure is substantially equal to or greater than the dimension of the barrier film;
- a first dielectric between the barrier film and the charge storage structure at a first side of the barrier film;
- and
- a second dielectric between the barrier film and the control gate at a second side of the barrier film opposite the first side of the barrier film.
A vertical stack of memory cells comprising a vertical pillar, wherein a cell of the stack comprises:
- a charge storage structure adjacent to the pillar along a dimension;
- a first dielectric and a barrier film adjacent to the charge storage structure along the dimension, the first dielectric between the charge storage structure and the pillar;
- a control gate adjacent to the dielectric and barrier film along the dimension, wherein the barrier film of the memory cell has a substantially uniform thickness across the entire dimension;
- a second dielectric between the barrier film and the charge storage structure at a first side of the barrier film;
- and
- a third dielectric between the barrier film and the control gate at a second side of the barrier film opposite the first side of the barrier film.
A vertical stack of memory cells, wherein a cell of the stack comprises:
- a charge storage structure having a dimension;
- a control gate having a dimension corresponding to the dimension of the charge storage structure, wherein the dimension of the control gate and the corresponding dimension of the charge storage structure are substantially equal;
- a barrier film between the charge storage structure and the control gate;
- a first dielectric between the barrier film and the charge storage structure at a first side of the barrier film;
- and
- a second dielectric between the barrier film and the control gate at a second side of the barrier film opposite the first side of the barrier film.
A vertical memory array comprising:
- a plurality of vertical memory strings, wherein a string of the plurality comprises:
- a vertical pillar;
- and
- at least two tier dielectric layers;
- and
- a memory cell between two adjacent tier dielectric layers of the at least two tier dielectric layers comprising:
- a charge storage structure having a dimension;
- a control gate;
- a dielectric layer between the charge storage structure and the vertical pillar;
- a barrier film between the charge storage structure and the control gate, the barrier film having a dimension corresponding to the dimension of the charge storage structure, the dimension of the barrier film and the dimension of the charge storage structure being substantially equal;
- a first dielectric between the barrier film and the charge storage structure at a first side of the barrier film;
- and
- a second dielectric between the barrier film and the control gate at a second side of the barrier film opposite the first side of the barrier film.
Dependencies are inferred from the claim text.