Memory cell with decoupled channels
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsShyue Seng Tan, Eng Huat Toh, Elgin Quek, Yanzhe Tang
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Abstract
A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.
Claims21
A device comprising:
- a substrate prepared with a memory cell region, the memory cell region comprises a memory cell, wherein the memory cell includes
- an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,
- an erase gate being disposed over the common S/D region, and
- a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.
A device comprising:
- a substrate prepared with a memory cell region, the memory cell region comprises at least one memory cell, wherein the at least one memory cell includes
- an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,
- an erase gate being disposed over the common S/D region, and
- a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.
A device comprising:
- a substrate with a memory cell region having at least one memory cell, wherein the at least one memory cell comprises
- an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,
- an erase gate being disposed over the common S/D region, wherein the erase gate is isolated from a storage and an access gate by gate sidewall dielectric layers, and
- a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.
Dependencies are inferred from the claim text.