Reduced area single poly EEPROM
AssigneeTexas Instruments Incorporated
InventorsJozef C. Mitros, Keith Jarreau, Pinghai Hao
Life of this patent
Estimating the term…
Abstract
A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.
Claims20
A single poly EEPROM cell, comprising:
- a control gate n-well
- a read gate dielectric layer located within said control gate n-well;
- a control gate dielectric layer also located within said control gate n-well;
- an erase gate n-well coupled to said control gate n-well,
- an erase gate dielectric layer located within said erase gate n-well, said erase gate dielectric being smaller than said control gate dielectric layer;
- and
- a floating gate that overlaps said control gate dielectric layer, said read gate dielectric layer, and said erase gate dielectric layer.
A single poly EEPROM cell, comprising:
- an erase gate n-well;
- a read gate dielectric located within said erase gate n-well;
- an erase gate dielectric layer also located within said erase gate n-well;
- a control gate n-well coupled to said erase gate n-well;
- a control gate dielectric layer located within said control gate n-well, said control gate dielectric layer being larger than said erase gate dielectric layer;
- and
- a floating gate that overlaps said erase gate dielectric layer, said read gate dielectric layer, and said control gate dielectric layer.
A method of forming a single poly EEPROM cell, comprising:
- providing a substrate;
- forming a control gate n-well in said substrate;
- forming an erase gate n-well in said substrate;
- forming a read gate dielectric layer over a portion of said control gate n-well;
- forming a control gate dielectric layer over a portion of said control gate n-well;
- forming an erase gate dielectric layer over a portion of said erase gate n-well, said erase gate dielectric layer being smaller than said control gate dielectric layer;
- and
- forming a floating gate over said control gate dielectric layer, said read gate dielectric layer, and said erase gate dielectric layer.
A method of forming a single poly EEPROM cell, comprising:
- providing a substrate;
- forming a control gate n-well in said substrate;
- forming an erase gate n-well in said substrate;
- forming a control gate dielectric layer over a portion of said control gate n- well;
- forming an read gate dielectric layer over a portion of said erase gate n-well;
- forming an erase gate dielectric layer over a portion of said erase gate n-well, said erase gate dielectric layer being smaller than said control gate dielectric layer;
- and
- forming a floating gate over said control gate dielectric layer, said read gate dielectric layer, and said erase gate dielectric layer.
Dependencies are inferred from the claim text.