Integrated circuits having replacement gate structures and methods for fabricating the same

A method of fabricating an integrated circuit comprising the steps of:

• forming an interlayer dielectric (ILD) layer over a dummy gate stack, the dummy gate stack formed over a semiconductor substrate and a dummy oxide layer formed over the semiconductor substrate, the dummy gate stack comprising a dummy gate structure, a hardmask disposed over the dummy gate structure, and sidewall spacers disposed along sides of the dummy gate structure and the hardmask and over the dummy oxide layer;
• removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, wherein removing at least the upper portion comprises removing the hardmask and portions of the sidewall spacers adjacent to the hardmask;
• forming a thin silicon nitride liner along the ILD layer within the first opening;
• extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack and a portion of the dummy oxide layer disposed thereunder, thereby exposing a portion of the semiconductor substrate;
• depositing a layer of a first workfunction material and a layer of a second workfunction material within the first opening and within the first extended opening;
• depositing an organic planarization layer within the first opening;
• removing portions of the first and second workfunction material layers within the first opening, using the organic planarization layer as an etch mask;
• removing the organic planarization layer;
• re-forming a portion of the sidewall spacers;
• depositing a low-resistance tungsten material over a remaining portion of the workfunction material layers and in between the re-formed portion of the sidewall spacers, thereby forming a replacement metal gate structure comprising the remaining portion of the workfunction material and the low-resistance material;
• and
• forming a capping layer over the replacement metal gate structure.