Semiconductor device with selectively etched surface passivation
AssigneeFreescale Semiconductor, Inc.
InventorsBruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Abstract
A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
Claims18
A semiconductor device comprising:
- a semiconductor substrate configured to include a channel;
- a gate supported by the semiconductor substrate to control current flow through the channel;
- a first dielectric layer supported by the semiconductor substrate and comprising an opening in which the gate is disposed;
- a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel;
- and
- first and second ohmic contacts spaced from one another and supported by the semiconductor substrate,
- wherein the second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel but not in a third area over the channel in which the second dielectric layer is disposed on the surface, the third area abutting one of the first and second ohmic contacts.
A heterostructure field effect transistor (HFET) device comprising:
- a semiconductor substrate comprising a base substrate and a Group III nitride semiconductor epitaxial layer supported by the base substrate and configured to include a channel, the semiconductor substrate further comprising at least one isolation region defining an active area along a surface of the semiconductor substrate;
- first and second ohmic contacts spaced from one another and supported by the semiconductor substrate in the active area;
- a gate supported by the semiconductor substrate to control current flow through the channel between the first and second ohmic contacts;
- a first dielectric layer extending between the first and second ohmic contacts and comprising an opening in which the gate is disposed to establish a Schottky junction at the surface of the semiconductor substrate;
- and
- a second dielectric layer disposed between the first dielectric layer and the surface of the semiconductor substrate in a first portion of the active area abutting the gate;
- wherein the second dielectric layer is patterned such that the first dielectric layer passivates the surface of the semiconductor substrate in a second portion of the active area but not in a third portion of the active area over the channel in which the second dielectric layer is disposed on the surface, the third portion abutting one of the first and second ohmic contacts.
Dependencies are inferred from the claim text.