Light emitting device, light emitting module, and method for manufacturing light emitting device

A method for manufacturing a light emitting device, comprising:

• forming a p-side interconnect layer on an interconnect surface of a stacked body, the stacked body including a plurality of semiconductor layers, a p-side electrode, an n-side electrode, and a first insulating layer, the plurality of semiconductor layers being partitionally separated by a dicing region, each of the plurality of semiconductor layers including a first surface, a second surface opposite to the first surface, and a light emitting layer provided between the first surface and the second surface, the p-side electrode being provided on the semiconductor layer, the n-side electrode being provided on the semiconductor layer, the first insulating layer being provided on the second surface side and having a first via communicating with the p-side electrode, a second via communicating with the n-side electrode, and an interconnect surface formed on a side opposite to the semiconductor layer;
• forming an n-side interconnect layer on the interconnect surface apart from the p-side interconnect layer;
• forming a second insulating layer between the p-side interconnect layer and the n-side interconnect layer;
• and
• exposing a portion of the p-side interconnect layer and a portion of the n-side interconnect layer at a third surface of a plane orientation different from the first surface and the second surface by cutting a region of the dicing region, the cut region of the dicing region including the second insulating layer, a portion of the p-side interconnect layer, and a portion of the n-side interconnect layer,
• the forming of the p-side interconnect layer including:
• forming a first p-side interconnect layer inside the first via and on the interconnect surface;
• and
• forming a second p-side interconnect layer in a recessed configuration on the first p-side interconnect layer, a portion of the second p-side interconnect layer having a U-shaped cross section, and exposed from the first insulating layer and the second insulating layer,
• the forming of the n-side interconnect layer including:
• forming a first n-side interconnect layer inside the second via and on the interconnect surface;
• and
• forming a second n-side interconnect layer in a recessed configuration on the first n-side interconnect layer, a portion of the second n-side interconnect layer having a U-shaped cross section, and exposed from the first insulating layer and the second insulating layer.

A light emitting device, comprising:

• a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer provided between the first surface and the second surface;
• a p-side electrode provided on the semiconductor layer;
• an n-side electrode provided on the semiconductor layer;
• a first insulating layer provided on the second surface side, the first insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode;
• a p-side interconnect layer including a first p-side interconnect layer electrically connected to the p-side electrode through the first via, and a second p-side interconnect layer electrically connected to the first p-side interconnect layer and provided on an interconnect surface provided on a side of the first insulating layer opposite to the semiconductor layer, the second p-side interconnect layer including a portion having an U-shaped cross section;
• an n-side interconnect layer including a first n-side interconnect layer electrically connected to the n-side electrode through the second via, and a second n-side interconnect layer electrically connected to the first n-side interconnect layer, separated from the p-side interconnect layer and provided on the interconnect surface, the second n-side interconnect layer including a portion having an U-shaped cross section;
• and
• a second insulating layer provided between the p-side interconnect layer and the n-side interconnect layer.