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US 8,946,726 B2Granted
Grid-UMOSFET with electric field shielding of gate oxide
AssigneeCree, Inc.
InventorsChristopher Harris, Andrei Konstantinov, Jan-Olov Svederg
Life of this patent
Estimating the term…
Abstract
A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.
Claims22
A semiconductor device comprising:
- a drift layer of a first conductivity type;
- a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type;
- a source layer of the first conductivity type on the channel layer;
- a source contact extending on the source layer;
- a trench extending through the source layer and the channel layer, and into the drift layer, so that a bottom of the trench is within the drift layer;
- a gate electrode within the trench;
- a buried region of the second conductivity type within the drift layer, the buried region extending laterally to include a portion directly underneath the trench so that a shallow region of the drift layer is between the bottom of the trench and the buried region;
- and
- a conductive via electrically connecting the source contact to the buried region.
6 more elements
A grid U-shape Metal Oxide Semiconductor Field Effect Transmitter (UMOSFET) comprising:
- a drift layer of a first conductivity type;
- a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type;
- a source layer of the first conductivity type on the channel layer;
- a source contact having a plurality of source contact fingers extending on the source layer substantially parallel with respect to each other;
- a plurality of trenches extending substantially parallel with respect to the plurality of source contact fingers, and through the source layer and the channel layer into the drift layer, so that bottoms of the plurality of trenches are within the drift layer;
- a plurality of gate electrodes respectively within the plurality of trenches;
- a plurality of buried regions of the second conductivity type within the drift layer, the plurality of buried regions respectively extending laterally to include a portion directly underneath the plurality of trenches so that shallow regions of the drift layer are between the bottoms of the plurality of trenches and the plurality of buried regions;
- and
- conductive vias electrically connecting the plurality of source contact fingers to the plurality of buried regions.
6 more elements
A semiconductor device comprising:
- a plurality of semiconductor layers;
- a trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) disposed within the plurality of semiconductor layers, the trench MOSFET comprising a trench for a gate contact;
- a long channel Junction Field Effect Transistor (JFET) including a buried region within a lowermost layer of the plurality of semiconductor layers, the buried region extending laterally to include a portion directly underneath the trench of the trench MOSFET so that a shallow region of the lowermost layer is between the trench of the trench MOSFET and the buried region;
- and
- the buried region of the long channel JFET is electrically coupled to a source potential applied to the trench MOSFET.
2 more elements
A semiconductor device comprising:
- a plurality of semiconductor layers;
- a trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) disposed within the plurality of semiconductor layers, the trench MOSFET comprising a trench for a gate contact;
- a buried region within a lowermost layer of the plurality of semiconductor layers, the buried region extending laterally to include a portion directly underneath the trench of the trench MOSFET so that a shallow region of the lowermost layer is between the trench of the trench MOSFET and the buried region;
- and
- the buried region is electrically coupled to a source potential applied to the trench MOSFET.
2 more elements
Dependencies are inferred from the claim text.