Structure and method for using high-K material as an etch stop layer in dual stress layer process

A semiconductor device comprising:

• a first conductivity type semiconductor device located in a first portion of a substrate;
• a second conductivity type semiconductor device located in a second portion of the substrate;
• an isolation region located in the substrate and separating the first portion of the substrate from the second portion of the substrate;
• a first high-k dielectric etch stop layer present over the first conductivity type semiconductor device and the second conductivity type semiconductor device;
• a first stress-inducing layer located on a portion of the at least one high-k dielectric etch stop layer that is over the first conductivity type semiconductor device, but not the second conductivity type semiconductor device;
• a second high-k dielectric etch stop layer present directly on a surface of the first stress-inducing layer located in the first portion of the substrate containing the first conductive type semiconductor device and directly on a surface of the first high-k dielectric etch stop layer in the second portion of the substrate containing the second conductivity type semiconductor device;
• and
• a second stress-inducing layer located on a portion of the second high-k dielectric etch stop layer that is over the second conductivity type semiconductor device, wherein second stress inducing layer extends over said isolation region and includes a protruding portion that has an entirely planar uppermost surface that is vertically offset from an exposed topmost surface of the second high-k dielectric etch stop layer that extends over the said isolation region.