Electrostatic discharge protection structure for an active array substrate

An electrostatic discharge protection structure positioned on an active array substrate, the electrostatic discharge protection structure comprising:

• a signal line;
• a first thin-film transistor, comprising:
• a first gate electrode electrically connected to the signal line;
• an insulating layer covering the first gate electrode, wherein the insulating layer has a first contact window;
• a first metal-oxide semiconductor layer comprising a first channel region that has a first width/length ratio of less than 1, the first metal-oxide semiconductor layer being disposed on the insulating layer;
• a first source electrode disposed on the first metal-oxide semiconductor layer and the insulating layer, wherein the first source electrode is equipotentially connected to the first gate electrode through the first contact window;
• and
• a first drain electrode disposed on the first metal-oxide semiconductor layer and the insulating layer, wherein the first source electrode and the first drain electrode are positioned at opposite sides of the first channel region;
• a shunt wire electrically connected to the first drain electrode, wherein when a voltage surge that exceeds a predetermined magnitude is applied to the signal line, the voltage surge is shunted through the first thin-film transistor to the shunt wire;
• a second thin-film transistor that electrically interconnects the first drain electrode and the shunt wire, wherein the second thin-film transistor comprises:
• a second gate electrode equipotentially connected to the first gate electrode;
• a second metal-oxide semiconductor layer comprising a second channel region that has a second width/length ratio of less than 1, the second metal-oxide semiconductor layer being disposed above the second gate electrode;
• a second source electrode equipotentially connected to the first drain electrode;
• and
• a second drain electrode equipotentially connected to the shunt wire;
• a third thin-film transistor which comprises:
• a third gate electrode equipotentially connected to the shunt wire;
• a third metal-oxide semiconductor layer comprising a third channel region that has a third width/length ratio of less than 1, the third metal-oxide semiconductor layer being disposed above the third gate electrode;
• a third source electrode equipotentially connected to the second drain electrode;
• and
• a third drain electrode connected to the third source electrode through the third metal-oxide semiconductor layer, wherein the third drain electrode is electrically connected to the signal line;
• and
• a fourth thin-film transistor that electrically interconnects the third drain electrode and the signal line, wherein the fourth thin-film transistor comprises:
• a fourth gate electrode equipotentially connected to the third gate electrode;
• a fourth metal-oxide semiconductor layer comprising a fourth channel region that has a fourth width/length ratio of less than 1, the fourth metal-oxide semiconductor layer being disposed above the fourth gate electrode;
• a fourth source electrode equipotentially connected to the third drain electrode;
• and
• a fourth drain electrode connected to the third source electrode through the fourth metal-oxide semiconductor layer, wherein the fourth drain electrode is equipotentially connected to the signal line.