Thin film transistor, array substrate and display device

An array substrate, comprising:

• a substrate;
• a thin film transistor formed on the substrate, wherein, the thin film transistor comprising:
• a gate layer, a first insulating layer, an active layer, an etch stop layer and a source/drain electrode layer, wherein
• the active layer is made of a metal oxide material,
• the first insulating layer, the active layer, the etch stop layer and the source/drain electrode layer are sequentially stacked from bottom to top,
• the source/drain electrode layer contains an interval separating a source electrode and a drain electrode therein, the etch stop layer is located below the interval, and the etch stop layer has a width greater than that of the interval,
• the first insulating layer comprises a laminate of a first sub-insulation layer and a second sub-insulation layer, the second sub-insulation layer is in contact with the active layer,
• the etch stop layer comprises a laminate of a first etch stop layer and a second etch stop layer the first etch stop layer is in contact with the active layer,
• the second sub-insulation layer is made of SiOx, the first sub-insulation layer is made of SiNx, and the first sub-insulation layer and the second sub-insulation layer are formed by a high temperature deposition method;
• the first etch stop layer is made of SiOx the second etch stop layer is made of SiNx, and the first etch stop layer and the second etch stop layer is formed by a low temperature deposition method,
• the first insulating layer has an extending portion extending to the outside of a region of the thin film transistor, and
• the array substrate further comprises a pixel electrode formed over the extending portion of the first insulating layer, the pixel electrode is in direct contact with the extending portion of the first insulating layer.

A thin film transistor, comprising:

• a gate layer, a first insulating layer, an active layer, an etch stop layer and a source/drain electrode layer, wherein
• the active layer is made of a metal oxide material,
• the first insulating layer, the active layer, the etch stop layer and the source/drain electrode layer are sequentially stacked from bottom to top,
• the source/drain electrode layer contains an interval separating a source electrode and a drain electrode therein, the etch stop layer is located below the interval, and the etch stop layer has a width greater than that of the interval, and
• the first insulating layer comprises a laminate of a first sub-insulation layer and a second sub-insulation layer, the second sub-insulation layer is in contact with the active layer and made of an oxygen-rich insulating material,
• the thin film transistor further comprising a second insulating layer disposed above the source/drain electrode layer, wherein the gate layer is disposed above the second insulating layer.