Vertical tunneling negative differential resistance devices
AssigneeIntel Corporation
InventorRavi Pillarisetty
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Abstract
The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.
Claims18
A microelectronic device, comprising:
- an upper quantum well;
- a lower quantum well separated from the upper quantum well by a barrier layer;
- a gate electrode proximate the upper quantum well;
- an upper quantum well contact coupled to the upper quantum well;
- and
- a lower quantum well contact coupled to the lower quantum well, wherein the lower quantum well contact extends through the upper quantum well and is electrically isolated therefrom with a dielectric material.
A method of fabrication a microelectronic device, comprising:
- forming a lower quantum well;
- forming a barrier layer proximate the lower quantum well;
- forming an upper quantum well proximate the barrier layer;
- forming a gate electrode proximate the upper quantum well;
- forming an upper quantum well contact coupled to the upper quantum well;
- and
- forming a lower quantum well contact coupled to the lower quantum well comprising:
- forming an opening through the upper quantum well;
- depositing a dielectric material on sidewalls of the opening;
- extending the opening through the barrier layer to expose a portion of the lower quantum well;
- and
- depositing a conductive material to fill the opening.
A system, comprising:
- an integrated circuit device;
- and
- a main memory;
- wherein at least one of said integrated circuit device and said main memory includes a microelectronic device comprising an upper quantum well, a lower quantum well separated from the upper quantum well by a barrier layer;
- a gate electrode proximate the upper quantum well;
- an upper quantum well contact coupled to the upper quantum well;
- and a lower quantum well contact coupled to the lower quantum well, wherein the lower quantum well contact extends through the upper quantum well and is electrically isolated therefrom with a dielectric material.
Dependencies are inferred from the claim text.