Three-dimensional semiconductor device, variable resistive memory device including the same, and method of manufacturing the same
AssigneeSK hynix Inc.
InventorNam Kyun Park
Life of this patent
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Abstract
A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3D semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the LDD region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain.
Claims13
A three-dimensional (3D) semiconductor device, comprising:
- a source formed of a first semiconductor material;
- a channel layer formed on the source and formed of the first semiconductor material;
- a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material;
- a drain formed on the LDD region and formed of the first semiconductor material;
- and
- a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain.
A variable resistive memory device, comprising:
- a semiconductor device including a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the LDD region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain;
- and
- a resistive memory structure electrically coupled to the drain of the semiconductor device.
Dependencies are inferred from the claim text.