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US 8,946,615 B2Granted
Image sensor circuit
AssigneeKabushiki Kaisha Toshiba
InventorJun Deguchi
Life of this patent
Estimating the term…
Abstract
The controlling circuit of the image censor circuit controls the row decoder to address the light receiving cell with the address signal to turn on the first MOS transistor and turns on the switch circuit with a switch controlling signal, and then controls the row decoder to turn off the first MOS transistor and then turns off the switch circuit with the switch controlling signal.
Claims20
An image sensor circuit, comprising:
- a column line connected to a sample holding terminal;
- a light receiving cell including a first MOS transistor that is connected between a power supply and the column line and receives an address signal at a gate thereof and a second MOS transistor that is connected in series with the first MOS transistor between the power supply and the column line and receives a voltage responsive to received light at a gate thereof;
- a row decoder that generates the address signal that addresses the light receiving cell;
- a sample holding circuit including a current source that is connected between the column line and a ground and outputs a constant current and a switch circuit connected in series with the current source between the column line and the ground;
- and
- a controlling circuit that controls the row decoder and the switch circuit of the sample holding circuit,
- wherein the controlling circuit
- controls the row decoder to address the light receiving cell with the address signal to turn on the first MOS transistor and turns on the switch circuit with a switch controlling signal, and then
- controls the row decoder to turn off the first MOS transistor and then turns off the switch circuit with the switch controlling signal.
6 more elements
An image sensor circuit, comprising:
- a column line connected to a sample holding terminal;
- a light receiving cell including a first MOS transistor that is connected between a power supply and the column line and receives an address signal at a gate thereof and a second MOS transistor that is connected in series with the first MOS transistor between the power supply and the column line and receives a voltage responsive to received light at a gate thereof;
- a row decoder that generates the address signal that addresses the light receiving cell;
- a sample holding circuit including a current source that is connected between the column line and a ground and outputs a constant current and a switch circuit connected in series with the current source between the column line and the ground;
- and
- a controlling circuit that controls the row decoder and the switch circuit of the sample holding circuit.
3 more elements
Dependencies are inferred from the claim text.