Packaging substrate having embedded through-via interposer and method of fabricating the same

A packaging substrate having an embedded through-via interposer, comprising:

• an encapsulant layer having opposite first and second surfaces;
• a through-via interposer embedded in the encapsulant layer and having opposite first and second sides and a plurality of conductive through-vias in communication with the first and second sides, wherein each of the conductive through-vias has a first end surface on the first side of the through-via interposer and a second end surface on the second side of the through-via interposer, the second side of the through-via interposer is exposed from the second surface of the encapsulant layer, the second side of the through-via interposer is flush with the second surface of the encapsulant, and the second end surfaces of the conductive through-vias protrude above the second side of the through-via interposer and the second surface of the encapsulant layer to serve as conductive bumps;
• a redistribution layer embedded in the encapsulant layer and formed on the first side of the through-via interposer and the first end surfaces of the conductive through-vias so as to electrically connect with the first end surfaces of the conductive through-vias, wherein the outermost layer of the redistribution layer has electrode pads;
• and
• a built-up structure formed on the second surface of the encapsulant layer, the second side of the through-via interposer and the conductive bumps, and having at least a dielectric layer, a circuit layer formed on the dielectric layer and a plurality of conductive vias formed in the dielectric layer for electrically connecting with the circuit layer, wherein portions of the conductive vias electrically connect with the conductive bumps, respectively.