US 8,946,084 B2 · Controlling the device performance by forming a stressed backside dielectric layer

Abstract

A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Claims17

Dependent claims

A method comprising:

pre-determining a target stress at a selected location in a semiconductor substrate of a wafer;
forming a through-substrate via (TSV) in the selected location;
finding a first stress applied to the selected location by the TSV;
selecting a material and process conditions for forming a dielectric layer that applies a second stress to the semiconductor substrate, wherein at the selected location, a combined stress of the first stress and a second stress is substantially equal to the target stress;
and
forming the dielectric layer on a backside of the semiconductor substrate using the material and the process conditions.

3 more elements

A method comprising:

forming a through-substrate via (TSV) extending from a front surface of a semiconductor substrate of a wafer into the semiconductor substrate, wherein the wafer comprises a transistor at the front surface of the semiconductor substrate, wherein the semiconductor substrate comprises a back surface opposite to the front surface, and wherein the TSV applies a first stress to a nearby region of the semiconductor substrate, with the nearby region being adjacent to the TSV;
performing a backside grinding on the back surface of the semiconductor substrate to expose the TSV;
forming a backside isolation layer over and contacting the back surface, wherein the TSV is exposed through the backside isolation layer;
forming a redistribution line on the backside of the semiconductor substrate, wherein the redistribution line is over the backside isolation layer;
and
forming a passivation layer comprising:
a first portion over the redistribution line;
a second portion on sidewalls of the redistribution line;
and
a third portion lower than the first portion and the second portion, wherein the passivation layer applies a second stress to the nearby region, with the second stress being of an opposite type than the first stress.

7 more elements

A method comprising:

forming a through-substrate via (TSV) extending from a front surface of a semiconductor substrate of a wafer into the semiconductor substrate, wherein the wafer comprises a transistor at the front surface of the semiconductor substrate, wherein the semiconductor substrate comprises a back surface opposite to the front surface, and wherein the TSV applies a first stress to a nearby region of the semiconductor substrate, with the nearby region being adjacent to the TSV;
performing a backside grinding on the back surface of the semiconductor substrate to expose the TSV;
forming a backside isolation layer over and contacting the back surface, wherein the TSV is exposed through the backside isolation layer;
forming a redistribution line on the backside of the semiconductor substrate, wherein the redistribution line is over the backside isolation layer;
and
forming a passivation layer comprising:
a first portion over the redistribution line;
a second portion on sidewalls of the redistribution line;
and
a third portion lower than the first portion and the second portion, wherein the passivation layer applies a second stress to the nearby region, with the second stress being of a same type as the first stress.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/042,154Filed 30 Sep 2013 · division

Priority

24 Aug 2011

Published

US 2014/0295582 A12 Oct 2014

Granted

3 Feb 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 64/011
Manufacture or treatment: of electrodes ohmically coupled to a semiconductor
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels

Controlling the device performance by forming a stressed backside dielectric layer

Life of this patent

Controlling the device performance by forming a stressed backside dielectric layer

Life of this patent

Abstract

Claims17