Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• forming a plurality of active regions separated from one another, on a substrate;
• forming a plurality of word lines across the plurality of active regions in a first direction and separated from one another in a second direction perpendicular to the first direction;
• forming a plurality of first contact plugs on the active regions, wherein the first contact plugs are insulated from an interlayer insulation layer;
• forming a plurality of bit lines electrically connected to the first contact plugs and across the word lines and a slender hole between the bit lines;
• forming a first insulation layer filling the slender hole between the bit lines;
• forming a plurality of first isolated holes separated from one another between the bit lines in the first direction and the second direction, by patterning the first insulation layer;
• forming a liner layer in the first isolated holes, wherein the liner layer compensates for a vertical profile of the first isolated holes and has an etching selectivity with respect to the first insulation layer;
• filling a second insulation layer in the first isolated holes on the liner layer, wherein the second insulation layer has an etching selectivity with respect to the first insulation layer;
• forming a plurality of second isolated holes between the bit lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer;
• and
• forming a second contact plug filling in the second isolated holes.

A method of manufacturing a semiconductor device, the method comprising:

• forming a device isolation trench having a plurality of device isolation regions therein in a substrate, thereby defining a plurality of active regions via the device isolation regions;
• forming a plurality of word line trenches in the substrate which extend parallel to one another and cross the active regions;
• sequentially forming a gate dielectric layer, a word line and a buried insulating layer in the word line trenches, wherein the word lines are disposed across the active regions in a first direction and are separated from one another in a second direction perpendicular to the first direction;
• forming a first interlayer insulation layer on the buried insulating layer;
• forming a second interlayer insulation layer on the first interlayer insulation layer;
• forming a plurality of direct contacts in the first and second interlayer insulation layers which are electrically connected to a source region of the active regions;
• forming a plurality of bit line stack structures which extend parallel to one another above the first and second interlayer insulation layers and the plurality of direct contacts, wherein the bit line stack structures include a plurality of bit lines disposed across the word lines and electrically connected to the direct contacts and a plurality of insulation capping lines that cover an upper surface of the bit lines, wherein the insulation capping lines are thicker than the bit lines;
• forming a plurality of slender holes between the bit lines of adjacent bit line stack structures;
• forming an insulation liner which covers exposed upper surfaces and exposed sidewalls of the bit line stack structures and an exposed upper surface of the second interlayer insulation layer;
• forming a plurality of spacers covering the insulation liner on opposing sidewalls of the bit line stack structures;
• forming a first insulation layer filling the slender holes between the adjacent bit line stack structures;
• forming a mask pattern on the bit line stack structures, the first insulation layer and the insulation liner, thereby exposing a portion of the first insulation layer via the mask pattern;
• etching the exposed portion of the first insulation layer using the mask pattern as an etching mask to form a plurality of patterned first insulation layers and a plurality of first isolated holes between the patterned first insulation layers and between the bit line stack structures, wherein the first isolated holes are separated from each other in the first and second directions by the patterned first insulation layers and the bit line stack structures;
• etching an exposed portion of the insulation liner using the mask pattern as an etching mask to form a patterned insulation liner;
• removing the mask pattern;
• forming a plurality of second insulation layers filling the first isolated holes after removing the mask pattern, wherein the second insulation layers have an etch selectivity with respect to the patterned first insulation layers;
• removing the patterned first insulation layers by using the etch selectivity between the second insulation layers and the patterned first insulation layers, thereby forming a plurality of second isolated holes between the bit line stack structures and between the second insulation layers, wherein the second isolated holes are separated from each other via the second insulation layers and the bit line stack structures;
• and
• forming a plurality of second contact plugs filling the second isolated holes.