Methods for producing a tunnel field-effect transistor

#The present invention relates generally to semiconductor devices, and more particularly to method for producing a tunnel field-effect transistor.

#The invention relates, inter alia, to a method for producing a field-effect transistor, in particular a tunnel field-effect transistor. The following steps are carried out in the method, without any restriction by the order in which the method steps are listed. A substrate is provided on which an auxiliary layer is arranged. The auxiliary layer is patterned by removing material of the auxiliary layer so as to produce at least one auxiliary region. A first spacer element is produced in a region in which material of the auxiliary layer has been removed. Using the first spacer element and the auxiliary region as a mask, a first connection region of a field-effect transistor is doped. The first connection region is covered with a covering material or a covering layer.

#The substrate is a monocrystalline semiconductor substrate, for example, in particular monocrystalline silicon. SOI substrates (silicon on insulator) are particularly suitable. The auxiliary layer comprises for example a different material than the substrate or the same material. Auxiliary layers composed of polycrystalline silicon are often used, from which gate electrodes of the transistor can be produced.

#Exemplary embodiments of the invention are explained below with reference to the accompanying drawings, in which:

#FIGS. 1 to 4 show production stages in the production of tunnel field-effect transistors in accordance with a first exemplary embodiment, in which a projection is produced at whose location gate regions are produced;

#FIG. 5 shows a production stage in the production of a tunnel field-effect transistor in accordance with a second exemplary embodiment, in which a projection is produced at which gate regions are produced;

#FIGS. 1 to 4 show production stages in the production of tunnel field-effect transistors T1 and T2 in accordance with a first exemplary embodiment. As is illustrated in FIG. 1, a monocrystalline semiconductor substrate 10, for example a silicon wafer, is taken as a starting point. The wafer surface is prepared, e.g., by cleaning. Isolation zones between adjacent transistors are subsequently produced, for example by the use of the LOCOS method (LOCal Oxidation) or by the use of shallow isolation trenches. As is shown in FIG. 1, shallow isolation trenches 32, 34 and 36 can be produced for separation between individual transistors T1, T2 of the integrated circuit arrangement. The isolation trenches 32 to 36 have for example a depth of 200 nm or of greater than 200 nm. The isolation trenches 32 to 36 are filled with silicon dioxide, for example. The isolation trench 34, for example, also makes it possible to achieve, in all the exemplary embodiments, a separation of the drain/source regions lying between the transistors produced in pairs, see e.g., drain/source region for the transistors T1 and T2.

#Channel implantations ensue, for example, by means of which, in particular, threshold voltages of the transistors are also predetermined. An insulating layer 12 is subsequently applied, which can be used as gate dielectric, for example by thermal oxidation. FIG. 2;

#After the application of the insulating layer 12, an auxiliary layer 14 is applied, for example composed of polycrystalline silicon. The thickness of the insulating layer 12 is for example only 2 nm (nanometers) or is less than 2 nm. The thickness of the auxiliary layer 14 is for example 50 nm or less. A resist is subsequently applied for example a photoresist. The resist is exposed and developed by means of a photolithographic method, a resist region 16 remaining which has a lateral extent L1 of for example 150 nm (nanometers) or less. The auxiliary layer 14 is patterned with the aid of the resist region, an auxiliary region 18 arising. The insulating layer 12 is also patterned at the same time or at a later point in time. During the patterning of the auxiliary layer 14, the process stops on the substrate 10 or on the insulating layer 12. Auxiliary regions 18 in other parts of the circuit arrangement are used for example as gate electrodes of planar CMOS field-effect transistors with connection regions having the same type of doping. The patterning of the auxiliary layer 14 is carried out for example by means of an anisotropic etching method, for example by means of an RIE method (Reactive Ion Etching). Optionally, a so-called trimming process can be carried out in which the lateral extent L1 of the auxiliary regions 18 is reduced further by means of an isotropic etching for example.