Methods of fabricating a semiconductor device including metal gate electrodes

A method of fabricating a semiconductor device, the method comprising:

• providing a semiconductor substrate having a first region and a second region;
• forming an insulation layer on the semiconductor substrate, the insulation layer formed with a first groove and a second groove;
• forming a laminated metal layer having a plurality of metal layers on the insulation layer;
• processing the laminated metal layer to have a first number of metal layers from the plurality of metal layers of the laminated metal layer in the first region by removing one of three metal layers of the plurality of metal layers, and a second number of metal layers from the plurality of metal layers of the laminated metal layer in the second region;
• forming a capping metal layer on the first number of metal layers in the first region and the second number of metal layers in the second region;
• and
• planarizing the capping metal layer with the first number of metal layers to form a first metal gate electrode in the first groove of the first region, and with the second number of metal layers to form a second metal gate electrode in the second groove of the second region,
• wherein the first metal gate electrode is formed as an alloy of a layer of the first number of metal layers in the first region and the capping metal layer in the first region.

A method of fabricating a semiconductor device, the method comprising:

• providing a semiconductor substrate having a first region and a second region;
• forming an insulating layer on the semiconductor substrate, the insulating layer being formed to include an interlayer insulating layer having first and second grooves respectively disposed in the first and second regions as well as a gate insulation layer covering at least bottom surfaces of the first and second grooves;
• forming a laminated metal layer haying a plurality of metal layers on the semiconductor substrate including the insulating layer;
• forming a planarization layer having non-photo sensitivity on the laminated metal layer, the planarization layer being formed to fill the first and second grooves;
• selectively removing the planarization layer in the first region using a dry etching process that uses argon gas as a process gas to expose at least a portion of the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region, and
• removing an uppermost metal layer of three metal layers of the plurality of metal layers of the laminated metal layer in the first region using the planarization layer pattern as an etch mask.

A method of fabricating a semiconductor device, the method comprising:

• providing a semiconductor substrate having a first region and a second region;
• forming an insulating layer on the semiconductor substrate, the insulating layer being formed to include an interlayer insulating layer having first and second grooves respectively disposed in the first and second regions as well as a gate insulation layer covering at least bottom surfaces of the first and second grooves;
• forming a laminated metal layer having a plurality of metal layers on the semiconductor substrate including the insulating layer;
• forming a planarization layer having non-photo sensitivity on the laminated metal layer, the planarization layer being formed to fill the first and second grooves;
• forming an inorganic anti-reflective layer pattern on the planarization layer, the inorganic anti-reflective layer pattern exposing the planarization in the first region;
• selectively removing the planarization layer in the first region using a dry etching process to expose at least a portion of the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region;
• and
• processing the laminated metal layer to have a first number of metal layers from the plurality of metal layers of the laminated metal layer in the first region by removing one of three metal layers of the plurality of metal layers using the planarization layer pattern as an etch mask, and a second number of metal layers from the plurality of metal layers of the laminated metal layer in the second region.

A method of fabricating a semiconductor device, the method comprising:

• providing a semiconductor substrate having a first region and a second region;
• forming an insulation layer on the semiconductor substrate, the insulation layer formed with a first groove and a second groove;
• forming a laminated metal layer having a plurality of metal layers on the insulation layer;
• processing the laminated metal layer to have a first number of metal layers from the plurality of metal layers of the laminated metal layer in the first region by removing one of three metal layers of the plurality of metal layers, and a second number of metal layers from the plurality of metal layers of the laminated metal layer in the second region;
• forming a capping metal layer on the first number of metal layers in the first region and the second number of metal layers in the second region;
• and
• planarizing the capping metal layer with the first number of metal layers to form a first metal gate electrode in the first groove of the first region, and with the second number of metal layers to form a second metal gate electrode in the second groove of the second region.

A method of fabricating a semiconductor device, the method comprising:

• providing a semiconductor substrate having a first region and a second region;
• forming an insulation layer on the semiconductor substrate, the insulation layer formed with a first groove and a second groove;
• forming a laminated metal layer having a plurality of metal layers on the insulation layer;
• processing the laminated metal layer by forming a planarization layer having non-photo sensitivity on the laminated metal layer, selectively removing the planarization layer in the first region, and removing an uppermost metal layer of three metal layers of the plurality of metal layers in the first region using the planarization layer remained in the second region as an etch mask to have a first number of metal layers from the plurality of metal layers of the laminated metal layer in the first region and a second number of metal layers from the plurality of metal layers of the laminated metal layer in the second region;
• forming a capping metal layer on the first number of metal layers in the first region and the second number of metal layers in the second region;
• and
• planarizing the capping metal layer with the first number of metal layers to form a first metal gate electrode in the first groove of the first region, and with the second number of metal layers to form a second metal gate electrode in the second groove of the second region.