Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same
AssigneeSamsung Display Co., Ltd.
InventorsByeong-Beom Kim, Je-Hyeong Park, Jae-Hyoung Youn, Jean-Ho Song, Jong-In Kim
Life of this patent
Estimating the term…
Abstract
A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
Claims13
A method for forming a barrier layer on a substrate through sputtering, comprising:
- forming the barrier layer at a power density in the range of approximately 1.5 W/cm2 to approximately 3 W/cm2, and at a pressure of an inert gas that is in the range of approximately 0.2 Pa to approximately 0.3 Pa, wherein the barrier layer has an amorphous structure, and wherein the barrier layer is disposed between a silicon layer and a copper layer.
A method for manufacturing a thin film transistor array panel, comprising:
- forming a gate electrode on an insulation substrate;
- forming a gate insulating layer on the gate electrode;
- forming a semiconductor on the gate insulating layer;
- forming an ohmic contact layer on the semiconductor;
- forming a data line and a drain electrode on the ohmic contact layer, the data line and the drain electrode including an amorphous barrier layer and a copper layer formed on the amorphous barrier layer;
- forming a passivation layer on the data line and the drain electrode;
- and
- forming a pixel electrode on the passivation layer, wherein the pixel electrode is connected to the drain electrode,
- wherein forming the data line and the drain electrode further comprises forming the barrier layer by sputtering, the sputtering being performed at a power density in the range of approximately 1.5 W/cm2 to approximately 3 W/cm2, and at a pressure of an inert gas that is in the range of approximately 0.2 Pa to approximately 0.3 Pa.
A method for manufacturing a thin film transistor array panel, comprising:
- forming a gate electrode on an insulation substrate;
- forming a gate insulating layer on the gate electrode;
- forming a semiconductor on the gate insulating layer;
- forming a barrier layer on the semiconductor by sputtering, wherein the barrier layer is an amorphous titanium layer;
- forming a data line, a source electrode, and a drain electrode, wherein the data line, the source electrode, and the drain electrode include a copper layer;
- forming a passivation layer on the data line, the source electrode, and the drain electrode;
- and
- forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode,
- wherein the sputtering is performed at a power density in the range of approximately 1.5 W/cm2 to approximately 3 W/cm2, and at a pressure of an inert gas that is in the range of approximately 0.2 Pa to approximately 0.3 Pa.
Dependencies are inferred from the claim text.