Integrated nanostructure-based non-volatile memory fabrication

A method of fabricating non-volatile memory with nanostructure charge storage regions, comprising:

• forming at least one peripheral transistor including a gate structure formed from a first conductive layer and a fourth conductive layer, the first conductive layer being separated from a substrate by a first dielectric layer;
• forming a plurality of storage elements including charge storage structures formed from a nanostructure layer separated from the substrate by a second dielectric layer, the storage elements having control gates formed from a second conductive layer separated from the nanostructure layer by a third dielectric layer;
• and
• forming at least one select gate for the plurality of storage elements including a gate structure formed from a third conductive layer, the third conductive layer being separated from the substrate by a fourth dielectric layer;
• wherein the first conductive layer is formed before the second conductive layer, the second conductive layer is formed before the third conductive layer, and the third conductive layer is formed before the fourth conductive layer;
• wherein the first dielectric layer is formed before the second dielectric layer, the second dielectric layer is formed before the third dielectric layer, and the third dielectric layer is formed before the fourth dielectric layer.