Methods of forming memory arrays and semiconductor constructions
AssigneeMicron Technology, Inc.
InventorsJaydip Guha, Shyam Surthi
Life of this patent
Estimating the term…
Abstract
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
Claims6
A method of forming a semiconductor construction, comprising:
- forming a heavily-doped region within a first semiconductor material;
- epitaxially growing a second semiconductor material over the first semiconductor material;
- patterning the second semiconductor material to form circuit components;
- patterning the heavily-doped region to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another;
- at least some of the patterning of the heavily-doped region occurring simultaneously with at least some of the patterning of the second semiconductor material;
- and wherein:
- the first semiconductor material is comprised by a semiconductor base;
- the heavily-doped region is formed in a memory array region of the base while protecting a region peripheral to the memory array region with a masking material, an upper surface of base within the memory array region being recessed relative to uppermost surfaces of the base within the peripheral region;
- the masking material is removed after forming the heavily-doped region;
- the second semiconductor material is epitaxially grown over both the memory array region and the peripheral region after removing the masking material;
- and
- a planarization process is performed after the epitaxial growth of the second semiconductor material to form a planarized surface across the memory array region and the peripheral region.
A method of forming a semiconductor construction, comprising:
- recessing into a memory array region of a semiconductor substrate to form a recessed memory array region relative to an upper surface of the semiconductor substrate in a region of the substrate peripheral to the memory array region;
- forming a heavily-doped region within the recessed memory array region;
- simultaneously epitaxially growing semiconductor material over the heavily-doped region and the peripheral region;
- performing a planarization process after the epitaxial growth of the second semiconductor material to form a planarized surface across the memory array region and the peripheral region;
- patterning the semiconductor material to form circuit components;
- patterning the heavily-doped region to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another;
- and
- at least some of the patterning of the heavily-doped region occurring simultaneously with at least some of the patterning of the semiconductor material.
Dependencies are inferred from the claim text.