Lateral diffusion field effect transistor with drain region self-aligned to gate electrode

A method manufacturing a semiconductor structure comprising:

• forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;
• forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;
• forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion;
• forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein said drain region is formed outside of an area occupied by said disposable conductive portion and an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion;
• removing said disposable conductive portion, while preserving said gate electrode;
• and
• wherein said dielectric gate spacer is of unitary construction and comprises said first portion, said second portion, and a third portion, wherein said first portion laterally abuts said gate electrode and does not abut said disposable conductive portion, said second portion laterally abuts said disposable conductive portion and does not abut said gate electrode, and a third portion laterally abuts said gate electrode and said disposable conductive portion.

A method manufacturing a semiconductor structure comprising:

• forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;
• forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;
• forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion;
• forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein said drain region is formed while said disposable conductive portion is present on said semiconductor substrate and an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion;
• removing said disposable conductive portion, while preserving said gate electrode;
• forming a drift region having a doping of a same conductivity type as said drain region within a surface portion of said semiconductor substrate by implanting dopants through an opening formed by removal of said disposable conductive portion, said drift region laterally contacting said drain region;
• and
• wherein said dielectric gate spacer is of unitary construction and comprises said first portion, said second portion, and a third portion, wherein said first portion laterally abuts said gate electrode and does not abut said disposable conductive portion, said second portion laterally abuts said disposable conductive portion and does not abut said gate electrode, and a third portion laterally abuts said gate electrode and said disposable conductive portion.