US 8,946,005 B2 · Thin-film transistor, array substrate having the thin-film transistor and method of manufacturing the array substrate

Abstract

A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Drawings

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Drawings

Claims9

Dependent claims

A method of manufacturing an array substrate, comprising:

providing a base substrate including a active region, a pixel region and wiring region;
forming an oxide semiconductor layer and a source metal layer on the base substrate, wherein the oxide semiconductor layer being disposed under the source metal layer;
patterning the source metal layer to form a source remaining pattern in the active region and a data line in the wiring region;
patterning the oxide semiconductor layer to form a first oxide semiconductor pattern in the active region and a second oxide semiconductor pattern in the wiring region;
patterning the source remaining pattern in the active portion to form a source electrode and a drain electrode such that the source electrode and the drain electrode are spaced apart from each other, the source electrode and the drain electrode substantially define an outline of the first oxide semiconductor pattern, and the data line substantially defines an outline of the second oxide semiconductor pattern;
forming a first insulation layer and a gate metal layer on the base substrate on which the source electrode, the drain electrode and the data line are disposed;
patterning the gate metal layer on the first insulation layer to form a gate pattern comprising a gate electrode in the active region and a gate line in the wiring region, the gate electrode being disposed on the first insulation layer, the gate line being electrically connected to the gate electrode and extended in a direction crossing the data line;
forming a second insulation layer on the base substrate on which the gate pattern is formed;
forming a contact hole extending from the second insulation layer to expose a portion of drain electrode;
forming a conductive layer on the second insulation layer and the portion of the drain electrode;
and
patterning the conductive layer to form a pixel electrode in the pixel portion such that the pixel electrode is electrically connected to the drain electrode through the contact hole.

9 more elements

Dependencies are inferred from the claim text.

Description14,911 words

Summary1,037 words

#1. Field of the Invention

#The present invention relates to a thin-film transistor, an array substrate having the thin-film transistor and a method of manufacturing the array substrate. More particularly, the present invention relates to a thin-film transistor capable of enhancing the display quality of a display apparatus, an array substrate having the thin-film transistor and a method of manufacturing the array substrate.

#2. Description of the Related Art

Brief description of the drawings19 figures

#The above and other aspects, features, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a layout illustrating an exemplary embodiment of a portion of an array substrate according to the present invention;

#FIG. 2 is a cross-sectional view illustrating an exemplary embodiment of an array substrate according to the present invention, which is taken along a line I-I′ in FIG. 1;

Detailed description13,354 words

#The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

#It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

#It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Facts

Application

13/030,213Filed 18 Feb 2011 · division

Priority

KR 2007-5835314 Jun 2007

Published

US 2011/0140103 A116 Jun 2011

Granted

3 Feb 2015

Term ends

31 Oct 2027

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification7 codes

H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks
H10D 86/40
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10D 86/423
Having a particular composition, shape or crystalline structure of the active layer: comprising semiconductor materials not belonging to the Group…

Timeline

14 Jun 2007Priority claimedKR 2007-58353
18 Feb 2011Application filedUS 13/030,213
16 Jun 2011PublishedUS 2011/0140103 A1
11 Oct 2012Assigned to Samsung Display Co., Ltd.assignment of assignor's interest
3 Feb 2015GrantedUS 8,946,005 B2
12 Oct 2026TodayWithin its term
31 Oct 2027Term endsEstimated

Thin-film transistor, array substrate having the thin-film transistor and method of manufacturing the array substrate

Life of this patent

Thin-film transistor, array substrate having the thin-film transistor and method of manufacturing the array substrate

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims9

Description14,911 words

Drawings

Classification7 codes

Life of this patent

Description14,911 words