Contact portion of wire and manufacturing method thereof

A method for manufacturing a thin film transistor array panel, the method comprising:

• forming a gate wire including a gate line, a gate electrode connected to the gate line, and a gate pad connected to one end of the gate line on a substrate;
• forming a gate insulating layer on the gate wire;
• forming a semiconductor layer on the gate insulating layer;
• forming a data wire intersecting and insulated from the gate line and including a data line, a source electrode connected to the data line and neighboring the gate electrode, a drain electrode facing the source electrode with respect to the gate electrode, and a data pad connected to one end of the data line;
• sequentially forming a lower insulating layer and an upper insulating layer on the data wire;
• patterning the upper insulating layer to form a first primary contact hole exposing the lower insulating layer;
• etching the lower insulating layer by using the patterned upper insulating layer as a mask to form a first contact hole exposing the drain electrode;
• selectively forming a first metal layer inside the first contact hole through electroless plating in a state that a width of the first contact hole in the upper insulating layer is smaller than that of the first contact hole of the lower insulating layer;
• and
• forming a pixel electrode on the upper insulating layer and connected to the first metal layer,
• wherein the forming the first metal layer inside the first contact hole includes forming the first metal layer having an upper surface of the first metal layer inside the first contact hole is higher-than an upper surface of the lower insulating layer, and
• wherein the forming the first metal inside the first contact hole through electroless plating includes filling the first contact hole having an undercut under the upper insulating layer with the first metal layer.