US 8,945,999 B2Granted

SRAM cell with different crystal orientation than associated logic

AssigneeTexas Instruments Incorporated

InventorTheodore W. Houston

Life of this patent

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Abstract

An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

Claims6

Dependent claims

A process of forming an integrated circuit, comprising:

providing a wafer, said wafer further including:
a substrate of a semiconductor material with a first crystal orientation;
and
a top layer of semiconductor material with a second crystal orientation formed over said substrate;
removing said top layer of semiconductor material in an SRAM region to expose said substrate;
growing an epitaxial layer of semiconductor material on said substrate in said SRAM region, wherein said epitaxial layer has said first crystal orientation;
forming an array of SRAM cells in said epitaxial layer in said SRAM region, in which each said SRAM cell further includes:
two SRAM NMOS transistors;
and
two SRAM PMOS transistors;
and
forming a logic circuit in said top layer of semiconductor material, said logic circuit further including:
a plurality of logic NMOS transistors;
and
a plurality of logic PMOS transistors, such that an average majority charge carrier mobility of said SRAM PMOS transistors is less than an average majority charge carrier mobility of said logic PMOS transistors.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/330,128Filed 14 Jul 2014 · division
Priority: 21 Apr 2009
Published: US 2014/0322870 A130 Oct 2014
Granted: 3 Feb 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H10B 10/00
Static random access memory [sram] devices
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels

Family

Application12/427,416Parent of this division · filed 21 Apr 2009
Application12/975,006Parent of this division · filed 21 Dec 2010
Application13/570,918Parent of this division · filed 9 Aug 2012
US 8,324,665 B2Parent of this division · filed 4 Dec 2012
US 8,535,990 B2Parent of this division · filed 17 Sep 2013
US 2014/0322870 A1Pre-grant publication · published 30 Oct 2014
US 2010/0264465 A1Published application
US 2011/0092029 A1Published application
US 2012/0302013 A1Published application
US 8,945,999 B2This patent

From the US filing history. Foreign family members aren’t listed.