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US 8,945,994 B2Granted
Single layer coreless substrate
AssigneeZhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
InventorsDror Hurwitz, Shih-Fu Alex Huang
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Abstract
An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.
Claims11
A method of fabricating an electronic chip package comprising the steps of:
- (a) selecting a sacrificial substrate;
- (b) depositing an etchant resistant barrier layer onto said sacrificial substrate;
- (c) plating a layer of via posts;
- (d) laminating the layer of via posts with a dielectric material;
- (e) thinning and planarizing the dielectric layer;
- (f) plating a layer of routing features over the via layer;
- (g) attaching at least one chip, and
- (h) encapsulating the at least one chip and routing features with a second dielectric material;
- (i) removing the sacrificial substrate, and
- (j) removing barrier layer.
7 more elements
Dependencies are inferred from the claim text.