Method of manufacturing a ball grid array substrate or a semiconductor chip package

#1. Field

#The present invention relates to a ball grid array substrate, a semiconductor chip package and a method of manufacturing the same, and more particularly, to a ball grid array substrate having an ultra-thin profile and including a high-density circuit pattern, a semiconductor chip package, and a method of manufacturing the same.

#2. Description of the Related Art

#The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIG. 1A is a schematic plan view illustrating a ball grid array substrate according to an exemplary embodiment of the present invention;

#FIG. 1B is a cross-sectional view taken along line A-A′ of FIG. 1, illustrating a part of the ball grid array substrate;

#Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the shapes and dimensions of elements are exaggerated for clarity. The same or equivalent elements are referred to by the same reference numerals throughout the specification.

#FIG. 1A is a schematic plan view illustrating a ball grid array substrate according to an exemplary embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line A-A′ of FIG. 1A, illustrating a part of the ball grid array substrate.

#Referring to FIGS. 1A and 1B, a ball grid array substrate 100, according to this exemplary embodiment, includes a first surface 111 providing a mounting region for a semiconductor chip, a second surface 112 opposing the first surface 111, an insulating layer having an opening 113 connecting the second surface with the mounting region for the semiconductor chip, and a circuit pattern 20 buried in the second surface 112.